# US 2014/0192584 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192584 A1 - Document ID: US20140192584A1 - Status: Published application - Kind: A1 - Application number: 13/846,381 - Filed: 2013-03-18 - Published: 2014-07-10 - Earliest claimed: 2013-01-07 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Seiichi ARITOME - Web page: https://patentgrep.com/patent/US20140192584A1 ## CPC - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 88/00: Three-dimensional [3D] integrated devices - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a first memory block including first vertical strings, a second memory block including second vertical strings coupled in series with the first vertical strings, wherein the second memory block is stacked on the first memory block, first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings, first source lines located under the first memory block and electrically coupled to the first vertical strings, and second source lines located above the second memory block and electrically coupled to the second vertical strings. ## Claims ### Claim 1 A semiconductor device, comprising: a first memory block including a plurality of first vertical strings; a second memory block including a plurality of second vertical strings electrically coupled in series with the plurality of first vertical strings, respectively, wherein the second memory block is stacked on the first memory block; first bit lines located between the first memory block and the second memory block and electrically coupled to the first and second vertical strings; a plurality of first source lines located under the first memory block and electrically coupled to the plurality of first vertical strings, respectively; and a plurality of second source lines located above the second memory block and electrically coupled to the second vertical strings, respectively. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first source lines and the second source lines extend in parallel along a first direction, respectively, and the first bit lines extend in parallel along a second direction crossing the first direction. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first bit lines, the first source lines and the second source lines extend in parallel along a first direction. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein source selection lines of the first and second memory blocks are controlled in common, and the first and second source lines are independently controlled. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein source selection lines of the first and second memory blocks are separately controlled, and the first and second source lines are separately controlled. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein source selection lines of the first and second memory blocks are separately controlled, and the first and second source lines are controlled in common. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising: a third memory block including a plurality of third vertical strings electrically coupled in series with the plurality of second vertical strings, respectively, wherein the third memory block is stacked on the second memory block; a fourth memory block including a plurality of fourth vertical strings electrically coupled in series with the plurality of third vertical strings, wherein the fourth memory block is stacked on the third memory block; a plurality of second bit lines located between the third memory block and the fourth memory block and electrically coupled to the plurality of third and the plurality of fourth vertical strings; and a plurality of third source lines located above the fourth memory block and electrically coupled to the plurality of fourth vertical strings. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the first to third source lines extend in parallel along a first direction, and the first and second bit lines extend in parallel along the second direction crossing the first direction. ### Claim 9 (depends on 7) The semiconductor device of claim 7, wherein the first and second bit lines and the first to third source lines extend in parallel along the first direction. ### Claim 10 (depends on 7) The semiconductor device of claim 7, wherein the first to fourth vertical strings include a plurality of control gates which are stacked in order, respectively, same order of control gates of the first to fourth vertical strings are electrically coupled in common, and the first to fourth memory blocks share an operating voltage supply circuit. ### Claim 11 (depends on 7) The semiconductor device of claim 7, wherein source selection lines of the first to fourth memory blocks are controlled in common, and the first to third source lines are separately controlled. ### Claim 12 (depends on 11) The semiconductor device of claim 11, further comprising: an operating circuit configured to apply a precharge voltage to bit lines coupled to a selected memory block, to apply a ground voltage to source lines coupled to the selected memory block, to apply a power voltage to other source lines, to apply a turn-on voltage to the source selection lines of the first to fourth memory blocks, to apply a turn-on voltage to a drain selection line electrically coupled to a selected vertical string, among vertical strings included in the selected memory block, and to apply a read voltage to a selected word line, during a read operation. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the operating circuit is configured to apply the ground voltage to drain selection lines electrically coupled to unselected vertical strings of the selected memory block, drain selection lines of unselected memory blocks and bit lines electrically coupled to the unselected memory blocks, respectively during a read operation. ### Claim 14 (depends on 11) The semiconductor device of claim 11, further comprising: an operating circuit configured to apply a precharge voltage to bit lines electrically coupled to a selected memory block, to apply a high voltage to a drain selection line electrically coupled to a selected vertical string among vertical strings included in the selected memory block, to apply a normal voltage the drain selection line when precharging of the bit lines is completed, to apply a ground voltage or a negative voltage is applied to source selection lines of the selected memory block, and to apply a program voltage to a selected word line, during a program operation. ### Claim 15 (depends on 11) The semiconductor device of claim 11, further comprising: an operating circuit configured to make a floating of bit lines a selected memory block, to apply an erase voltage to source lines electrically coupled to a selected memory block, to apply a ground voltage to other source lines, to apply the ground voltage a drain selection line coupled to a selected vertical string among vertical strings of the selected memory block, to apply the erase voltage is applied to a source selection line electrically coupled to the selected vertical string, and to apply a negative voltage to selected word lines, during an erase operation. ### Claim 16 (depends on 11) The semiconductor device of claim 11, wherein the operating circuit is apply the erase voltage to source select lines of unselected memory blocks, during an erase operation. ### Claim 17 (depends on 7) The semiconductor device of claim 7, wherein the source selection lines of the first to fourth memory blocks are separately controlled, and the first to third source lines are separately controlled. ### Claim 18 (depends on 17) The semiconductor device of claim 17, further comprising: an operating circuit configured to apply a precharge voltage to bit lines electrically coupled to a selected memory block, to apply a ground voltage to source lines electrically coupled to the selected memory block, to apply a turn-on voltage to drain selections line of the selected memory block, to apply the turn-on voltage to a source selection line of the selected memory block, to apply a read voltage to a selected word line, to apply a power voltage to bit lines coupled to unselected memory blocks, to apply the power voltage or the ground voltage to source lines coupled to the unselected memory blocks, to apply the turn-on voltage or the ground voltage to drain selection lines of the unselected memory blocks, and to apply the ground voltage or the power voltage to source selection lines of the unselected memory blocks, during a read operation. ### Claim 19 (depends on 7) The semiconductor device of claim 7, wherein the source selection lines of the first to fourth memory blocks are separately controlled, and the first to third source lines are equally controlled. ### Claim 20 (depends on 19) The semiconductor device of claim 19, further comprising: an operating circuit is configured to apply a precharge voltage to bit lines electrically coupled to a selected memory block, to apply a ground voltage to the first to third source lines, to apply a turn-on voltage to a drain selection line electrically coupled to a selected vertical string among vertical strings included in the selected memory block, to apply a turn-on voltage to a source selection line coupled to the selected vertical string and to apply a read voltage is applied to a selected word line, during a read operation.