# US 2014/0192583 A1 · Configurable memory circuit system and method

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- Number: US 2014/0192583 A1
- Document ID: US20140192583A1
- Status: Published application
- Kind: A1
- Application number: 14/090,342
- Filed: 2013-11-26
- Published: 2014-07-10
- Earliest claimed: 2005-06-24
- Assignees: Google Inc.
- Inventors: Suresh Natarajan Rajan; Keith R. Schakel; Michael John Sebastien Smith; David T. Wang; Frederick Daniel Weber
- Web page: https://patentgrep.com/patent/US20140192583A1

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G11C 29/808: {using a flexible replacement scheme}
- G11C 2029/0409: {Online test}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

## Claims

### Claim 1

A sub-system, comprising:
an interface circuit adapted for coupling with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.