# US 2014/0192582 A1 · Memory structure with reduced number of reflected signals

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- Number: US 2014/0192582 A1
- Document ID: US20140192582A1
- Status: Published application
- Kind: A1
- Application number: 13/738,129
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Eorex Corporation
- Applicants: Eorex Corporation
- Inventors: Cheng-Lung LIN
- Web page: https://patentgrep.com/patent/US20140192582A1

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.

## Claims

### Claim 1

A memory structure with reduced-reflection signals, at least comprising:
a processing unit;
a lumped circuit unit, connected to the processing unit;
a plurality of memories, connected to the lumped circuit unit; and
a reflected signal absorption unit, disposed at one end of the lumped circuit unit.

### Claim 2 (depends on 1)

The memory structure of claim 1, wherein each memory comprises an address circuit, a command circuit and a control circuit which are respectively connected to the lumped circuit unit.

### Claim 3 (depends on 1)

The memory structure of claim 1, wherein each memory is individually connected to the lumped circuit unit.

### Claim 4 (depends on 1)

The memory structure of claim 1, wherein each memory is disposed on a chip to form a memory chip which is connected to the lumped circuit unit.

### Claim 5 (depends on 4)

The memory structure of claim 4, wherein at a front end of the lumped circuit unit is disposed another reflected signal absorption unit.

### Claim 6 (depends on 1)

The memory structure of claim 1, wherein the reflected signal absorption unit is disposed is a resister.

### Claim 7 (depends on 1)

The memory structure of claim 1, wherein when the processing unit, the lumped circuit unit, each memory and the reflected signal absorption unit is in the circuit layout, at least two address/control/command areas is provided between the processing unit and the lumped circuit unit; each memory is located on both sides of each address/control/command areas; between the lumped circuit unit and each memory is provided a ground area; and a plurality of power lines is provided between each memory and the processing unit.

### Claim 8 (depends on 5)

The memory structure of claim 5, wherein the reflected signal absorption unit is disposed is a resister.