# US 2014/0192581 A1 · Programmable and flexible reference cell selection method for memory devices

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- Number: US 2014/0192581 A1
- Document ID: US20140192581A1
- Status: Published application
- Kind: A1
- Application number: 13/737,321
- Filed: 2013-01-09
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: Spansion LLC
- Applicants: Spansion LLC
- Inventors: Michael Achter; Evrim Binboga; Harry Kuo
- Web page: https://patentgrep.com/patent/US20140192581A1

## CPC

- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/0491: {Virtual ground arrays}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

## Claims

### Claim 1

A system, comprising:
an array of interconnected cells configured to:
receive a selection signal as input;
select a cell based upon the selection signal; and
provide an output based upon the selected cell; and
a flexible decoder configured to:
receive an input;
generate a selection signal based on the input and one or more characteristics of the array of interconnected cells; and
provide the selection signal to the array of interconnected cells.

### Claim 2 (depends on 1)

The system of claim 1, wherein the array of interconnected cells includes a reference array of reference sources; and
wherein the output is a reference current or voltage.

### Claim 3 (depends on 1)

The system of claim 1, wherein the array of interconnected cells includes an array of sensor cells; and
wherein the output is output from a sensor cell.

### Claim 4 (depends on 1)

The system of claim 1, wherein the program instructions and processor are configured to receive input in the form of a detectable environmental condition.

### Claim 5 (depends on 2)

The system of claim 2, further comprising:
a memory array of interconnected memory cells; and
at least one comparator configured to:
receive a signal from the reference array and a signal from the memory array; and
determine the state of at least one memory cell by comparing the signals from the reference array and the memory array.

### Claim 6 (depends on 5)

The system of claim 5, wherein the flexible decoder is further configured to:
provide signals to the memory array and the reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

### Claim 7 (depends on 5)

The system of claim 5, wherein the flexible decoder is further configured to:
receive input in the form of a detectable environmental condition; and
perform at least one of the following operations on the memory array based on the received input: read, program/write, and erase.

### Claim 8 (depends on 5)

The system of claim 5, wherein the flexible decoder is further configured to:
perform periodic monitoring of the memory array to detect errors; and
perform refresh operations to correct errors.

### Claim 9

A method of conditioning a reference array, comprising:
receiving an input;
generating a selection signal, based on the input and one or more characteristics of a reference array of interconnected reference sources;
providing the selection signal to the reference array, wherein the reference array provides a reference current or voltage as output corresponding to the selection signal;
repeating the receiving, generating, and providing steps for a plurality of inputs to determine a relationship between the inputs and their respective output currents or voltages; and
changing the generation of selection signals so as to change the relationship between the plurality of inputs and their respective output currents or voltages.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
receiving input in the form of a detectable environmental condition.

### Claim 11

A method, comprising:
receiving an input;
generating, based on the input and one or more characteristics of a reference array of interconnected reference sources, a selection signal; and
providing the selection signal to the reference array, wherein the reference array provides a reference current or voltage as output corresponding to the selection signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
receiving input in the form of a detectable environmental condition.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
generating and providing an input signal to a memory array of interconnected memory cells;
receiving an output signal from the memory array; and
determining the state of at least one memory cell by comparing the output signal from the reference array with the reference current or voltage from the reference array.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
providing signals to the memory array and reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
receiving input in the form of a detectable environmental condition; and
performing one of the following operations on the memory array based on the received input: read, program/write, and erase.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
performing periodic monitoring of the memory array to detect errors; and
performing refresh operations to correct errors.

### Claim 17

A non-transitory computer readable storage medium having program instructions stored thereon that, when executed by a processor, cause the processor to perform operations, the operations comprising:
receiving an input;
generating a selection signal based on the input; and
providing the selection signal to a reference array of interconnected reference sources to cause the array to provide a reference current or voltage as output.

### Claim 18 (depends on 17)

The computer readable storage medium of claim 17, wherein the operations further comprise:
receiving input in the form of a detectable environmental condition.

### Claim 19 (depends on 17)

The computer readable storage medium of claim 17, wherein the operations further comprise:
generating and providing an input signal to a memory array of interconnected memory cells; receiving an output signal from the memory array; and
determining the state of at least one memory cell by comparing the output signal from the reference array with the reference current or voltage from the reference array.

### Claim 20 (depends on 17)

The computer readable storage medium of claim 17, wherein the operations further comprise:
providing signals to the memory array and reference array so as to perform at least one of the following operations on the memory array: read, program/write, and erase.

### Claim 21 (depends on 19)

The computer readable storage medium of claim 19, wherein the operations further comprise:
receiving input in the form of a detectable environmental condition; and
performing at least one of the following operations on the memory array based on the received input: read, program/write, and erase.

### Claim 22 (depends on 19)

The computer readable storage medium of claim 19, wherein the operations further comprise:
performing periodic monitoring of the memory array to detect errors; and
performing refresh operations to correct errors.