# US 2014/0192579 A1 · Two phase search content addressable memory with power-gated main-search > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192579 A1 - Document ID: US20140192579A1 - Status: Published application - Kind: A1 - Application number: 13/733,973 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Igor Arsovski; Michael T. Fragano; Travis R. Hebig - Web page: https://patentgrep.com/patent/US20140192579A1 ## CPC - G11C 15/04: using semiconductor elements - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations. ## Claims ### Claim 1 A content addressable memory, comprising: an array of content addressable memory cells arranged in rows and columns and partitioned into a pre-search section and a main-search section; and each row of content addressable memory cells including: a row of content addressable memory cells of said pre-search section connected between a first positive voltage rail and ground and connected to a pre-matchline of said content addressable memory; a corresponding row of content addressable memory cells of said main-search section connected to a light-sleep circuit, to ground and to a main-matchline of said content addressable memory, said light-sleep circuit configured to connect content addressable memory cells of said main-search section to a second positive voltage rail in a light-sleep state and to connect content addressable memory cells of said corresponding row of content addressable memory cells of said main-search section to said first positive voltage rail in an awake state; a pre-search circuit connected to a pre-search matchline and (i) configured to perform a pre-search of said row of content addressable memory cells of said pre-search section and (ii) configured, only if a match is found, place said light-sleep circuit in said awake state; and a main-search circuit connected to a main matchline and configured to activate a main-search of said row of content addressable memory cells of said main-search section only if a match is found by said corresponding pre-search circuit. ### Claim 2 (depends on 1) The content addressable memory of claim 1, wherein said light-sleep circuits are configured to place content addressable memory cells of said main-search section in said awake state when a read or write operation is performed to said content addressable memory. ### Claim 3 (depends on 1) The content addressable memory of claim 1, wherein said first positive voltage is greater than said second positive voltage. ### Claim 4 (depends on 1) The content addressable memory of claim 1, wherein content addressable memory cells are ternary content addressable memory cells. ### Claim 5 (depends on 4) The content addressable memory of claim 4, wherein said ternary content addressable memory cells comprise: a first six cell static random access memory cell connected between a first wordline and a matchline and connected between a first bitline and a second bitline; a second six cell static random access memory cell connected between a first wordline and said matchline and connected between said first bitline and said second bitline; a first NOR pull-down stack connected to said first six cell static random access memory cell, said matchline and a first search line; and a second NOR pull-down stack connected to said second six cell static random access memory cell, said matchline and a second search line. ### Claim 6 (depends on 1) The content addressable memory of claim 1, wherein content addressable memory cells are binary content addressable memory cells. ### Claim 7 (depends on 6) The content addressable memory of claim 6, wherein said binary content addressable memory cells comprise: a six cell static random access memory cell connected between a wordline and a matchline and connected between a first bitline and a second bitline; a first NOR pull-down stack connected to said six cell static random access memory cell, said matchline and a first search line; and a second NOR pull-down stack connected to said six cell static random access memory cell, said matchline and a second search line. ### Claim 8 (depends on 1) The content addressable memory of claim 1, further including: a search data register/driver connected to search lines of said content addressable memory; and an address encoder connected to match result lines of said content addressable memory. ### Claim 9 (depends on 1) The content addressable memory of claim 1, wherein said content addressable memory cells of said main-search section include a pair of cross-coupled inverters, PFETs of said invertors connected to a voltage output of said light-sleep circuits and NFETs of said inverters connected to ground. ### Claim 10 (depends on 1) The content addressable memory of claim 1, further including: a respective latch connected to an output of each of said main-search circuits. ### Claim 11 A method of searching a content addressable memory, comprising: providing an array of content addressable memory cells arranged in rows and columns and partitioned into a pre-search section and a main-search section; applying a first positive voltage to content addressable memory cells of said pre-search section; applying a second positive voltage to content addressable memory cells of said main-search section, said second voltage lower than said first voltage; applying a search word comprising a set of pre-search bits and main-search bits to said content addressable memory; performing a pre-search of each row of content addressable memory cells of said pre-search section using said set of pre-search bits; only for each row of content addressable memory cells where a match was found as a result of performing said pre-search, de-applying said second voltage and applying said first voltage to said content addressable memory cells of said main-search section and then performing a main-search of those rows of content addressable memory cells of said main-search section using said set of main-search bits; for each row of content addressable memory cells where no match was found as a result of performing said pre-search or as a result of performing said main-search, generating a no-match signal; and for each row of content addressable memory cells where a match was found as a result of performing said pre-search and as a result of performing said main-search, generating a match signal. ### Claim 12 (depends on 11) The method of claim 11, further including: de-applying said second voltage and applying said first voltage to said content addressable memory cells of said main-search section after completion of said main-search. ### Claim 13 (depends on 11) The method of claim 11, further including: de-applying said second voltage and applying said first voltage to said content addressable memory cells of said main-search section so as to perform a read operation to said content addressable memory at said first voltage or to perform a read operation of said content addressable memory performed or a sequence of read and write operations; and de-applying said first voltage and applying said second voltage to said content addressable memory cells of said main-search section after completion of said read operation or said write operation or said sequence of read and write operations. ### Claim 14 (depends on 11) The method of claim 11, wherein content addressable memory cells are ternary content addressable memory cells. ### Claim 15 (depends on 14) The method of claim 14, wherein said ternary content addressable memory cells comprise: a first six cell static random access memory cell connected between a first wordline and a matchline and connected between a first bitline and a second bitline; a second six cell static random access memory cell connected between a first wordline and said matchline and connected between said first bitline and said second bitline; a first NOR pull-down stack connected to said first six cell static random access memory cell, said matchline and a first search line; and a second NOR pull-down stack connected to said second six cell static random access memory cell, said matchline and a second search line. ### Claim 16 (depends on 11) The method of claim 11, wherein content addressable memory cells are binary content addressable memory cells. ### Claim 17 (depends on 16) The method of claim 16, wherein said binary content addressable memory cells comprise: a six cell static random access memory cell connected between a wordline and a matchline and connected between a first bitline and a second bitline; a first NOR pull-down stack connected to said six cell static random access memory cell, said matchline and a first search line; and a second NOR pull-down stack connected to said six cell static random access memory cell, said matchline and a second search line. ### Claim 18 (depends on 11) The method of claim 11, further including: applying said search word to all rows of said content addressable memory simultaneously; and encoding the address of each row of said content addressable memory that generated a match signal. ### Claim 19 (depends on 11) The method of claim 11, further including: latching each match or no match signal. ### Claim 20 (depends on 11) The method of claim 11, wherein: each row of content addressable memory cells includes: a row of content addressable memory cells of said pre-search section connected between a first positive voltage rail and ground and connected to a pre-matchline of said content addressable memory; a corresponding row of content addressable memory cells of said main-search section connected to a light-sleep circuit, to ground and to a main-matchline of said content addressable memory of said main-search section, said light-sleep circuit configured to connect content addressable memory cells to a second positive voltage rail in a light-sleep state and to connect content addressable memory cells of said corresponding row of content addressable memory cells of said main-search section to said first positive voltage rail in an awake state; a pre-search circuit connected to a pre-search matchline and (i) configured to perform a pre-search of said row of content addressable memory cells of said pre-search section and (ii) configured, only if a match is found, place said light-sleep circuit in said awake state; and a main-search circuit connected to a main matchline and configured to activate a main-search of said row of content addressable memory cells of said main-search section only if a match is found by said corresponding pre-search circuit. ### Claim 21 (depends on 20) The method of claim 20, wherein said content addressable memory cells of said main-search section include a pair of cross-coupled inverters, PFETs of said invertors connected to a voltage output of said light-sleep circuits and NFETs of said inverters connected to ground.