# US 2014/0192560 A1 · Duty cycle balance module for switch mode power converter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0192560 A1
- Document ID: US20140192560A1
- Status: Published application
- Kind: A1
- Application number: 13/735,481
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Analog Devices Technology
- Applicants: Analog Devices Technology
- Inventors: YINGYANG OU; RENJIAN XIE; HUAILIANG SHENG
- Web page: https://patentgrep.com/patent/US20140192560A1

## CPC

- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 1/40: Means for preventing magnetic saturation
- H02M 3/33507: {with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence)}
- H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74)
- H02M 3/33576: {having at least one active switching element at the secondary side of an isolation transformer}
- H02M 7/4803: {with means for reducing DC component from AC output voltage}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A duty cycle balance module (DCBM) for use with a switch mode power converter. One possible half-bridge converter embodiment includes a transformer driven to conduct current in first and second directions by first and second signals during and second half-cycles, respectively. A current limiting mechanism adjusts the duty cycles of the first and second signals when a sensed current exceeds a predetermined limit threshold. The DCBM receives signals representative of the duty cycles which would be used if there were no modification by the current limiting mechanism and signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for the first and second signals, and outputs signals Dbl—1 and Dbl—2 which modify signals Dact—1 and Dact—2 as needed to dynamically balance the duty cycles of the first and second signals and thereby reduce flux imbalance in the transformer that might otherwise arise.

## Claims

### Claim 1

A duty cycle balance module for a switch mode power converter which includes an electromagnetic component that is driven to conduct current in a first direction during a first half-cycle by a first signal having an associated on- and off-time during each first half-cycle or by a third signal and fourth signal having a common ON time during each first half-cycle, and in a second direction during a second half-cycle by a second signal having an associated on- and off-time during each second half-cycle or by a fifth signal and sixth signal having a common ON time during each second half-cycle to achieve a desired result, said first and second half-cycles having associated periods, said first and second half-cycles constituting a switching cycle, said first, second, third, fourth, fifth and sixth signals having associated duty cycles respectively defined as the ratio of their respective ON times to the period of said switching cycle, and which further includes a current limiting mechanism which senses a current in said converter and adjusts the duty cycles of at least one of said first, second, third, fourth, fifth, and sixth signals when said sensed current exceeds a predetermined limit threshold, said duty cycle balance module comprising:
an input block which receives signals Dnor—1 and Dnor—2 representative of the duty cycles or ON times which would be used for said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals, respectively, to achieve said desired result if said duty cycles were not modified by said current limiting mechanism, and signals Dact—1 and Dact—2 representative of the duty cycles or ON times that are actually used for said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals; and
an output block which provides output signals Dbl—1 and Dbl—2, said duty cycle balance module arranged such that Dbl—1 and Dbl—2 modify said signals Dact—1 and Dact—2 as needed in response to said received signals so as to dynamically balance the duty cycles used for said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals and thereby reduce the magnetic flux imbalance in said electromagnetic component that might otherwise arise.

### Claim 2 (depends on 1)

The duty cycle balance module of claim 1, wherein said switch mode power converter has a half bridge, full-bridge or push-pull topology and said electromagnetic component is a transformer.

### Claim 3 (depends on 1)

The duty cycle balance module of claim 1, wherein said electromagnetic component is a motor.

### Claim 4 (depends on 1)

The duty cycle balance module of claim 1, wherein said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals are pulse-width modulated (PWM) signals.

### Claim 5 (depends on 1)

The duty cycle balance module of claim 1, wherein said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals are pulse-frequency modulated (PFM) signals.

### Claim 6 (depends on 1)

The duty cycle balance module of claim 1, wherein at least one of said first and said second signals, or said third and said fifth signals, or said third and said sixth signals, or said fourth and said fifth signals, or said fourth and said sixth signals are fixed width signals.

### Claim 7 (depends on 1)

The duty cycle balance module of claim 1, wherein said current limiting mechanism includes a cycle-by-cycle limit module which receives signals Dbl—1 and Dbl—2 which are equal to or derived from said signals Dnor—1 and Dnor—2 and a signal representative of said sensed current as inputs, and which provides said signals Dact—1 and Dact—2 as outputs, said cycle-by-cycle limit module arranged to terminate the signal Dact—1 during said first half-cycle if said sensed current exceeds said predetermined limit threshold during said first half-cycle and to terminate signal Dact—2 during said second half-cycle if said sensed current exceeds said predetermined limit threshold during said second half-cycle.

### Claim 8 (depends on 7)

The duty cycle balance module of claim 7, wherein the amount of duty cycle lost or ON time lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost or ON time lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch or ON time mismatch Dmis is given by:
Dmis=|ΣDloss1−ΣDloss2|,
said duty cycle balance module arranged to provide an output Dbl—1 during said first half-cycle given by:
Dbl—1=Dnor—1−Dmis
and an output Dbl—2 during said second half-cycle given by:
Dbl—2=Dnor—2−Dmis,
said signals Dbl—2 and Dbl—2 provided to said cycle-by-cycle limit module.

### Claim 9 (depends on 8)

The duty cycle balance module of claim 8, said duty cycle balance module further arranged such that when Dbl—1≧Dnor—1 and Dbl—2≧Dnor—2, or Dmis=0, indicating that there is no duty cycle or ON time imbalance, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 10 (depends on 7)

The duty cycle balance module of claim 7, wherein the amount of duty cycle lost or ON time lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost or ON time lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch or ON time mismatch Dmis is given by:
Dmis=|ΣDloss—1−ΣDloss—2|,
said duty cycle balance module arranged such that, when said sensed current exceeds said predetermined limit threshold during said first or second half-cycles, a value Dini is set to the value of the duty cycle or ON time Dact as adjusted during the half-cycle that the predetermined limit threshold was exceeded and a value k is set to 0, said duty cycle balance module arranged to provide outputs Dbl—1[k] and Dbl—2[k] given by:
Dbl—1[k]=Dbl—1[k−1]+Dinc and Dbl—2[k]=Dbl—2[k−1]+Dinc,
where Dbl—1[k] and Dbl—2[k] are the outputs of the duty cycle balance module during the current half-cycle, Dbl—1[k−1] and Dbl—2[k−1] are the outputs of the duty cycle balance module during the previous half-cycle, Dbl—1[0]=Dini and Dbl—2[0]=Dini, Dinc is a fixed or variable duty cycle or ON time increment value, and k is incremented by 1 every half-cycle, said signals Dbl—1[k] and Dbl—2[k] provided to said cycle-by-cycle limit module.

### Claim 11 (depends on 10)

The duty cycle balance module of claim 10, said duty cycle balance module further arranged such that, when Dbl—1[k]≧Dnor—1[k] and Dbl—2[k]≧Dnor—2 or Dmis=0, indicating that there is no duty cycle or ON time imbalance, Dbl—1[k]=Dnor—1[k], Dbl—2[k]=Dnor—2[k], and said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 12 (depends on 7)

The duty cycle balance module of claim 7, wherein the amount of duty cycle lost or ON time lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost or ON time lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch or ON time mismatch Dmis is given by:
Dmis=|ΣDloss—1−ΣDloss—2|,
said duty cycle balance module arranged such that, when said sensed current exceeds said predetermined limit threshold during said first or second half-cycles, a value Dpre is set to the value of the duty cycle or ON time Dact as adjusted during the half-cycle that the predetermined limit threshold was exceeded, and said duty cycle balance module provides an output Dbl in the next half-cycle given by:
Dbl—1=Dpre or Dbl—2=Dpre;
and when said sensed current does not exceed said predetermined limit threshold during the previous half-cycle, said duty cycle balance module provides an output Dbl in the next half-cycle given by:
Dbl—1=Dnor—1 or Dbl—2=Dnor—2;
said signals Dbl—1 and Dbl—2 provided to said cycle-by-cycle limit module.

### Claim 13 (depends on 12)

The duty cycle balance module of claim 12, said duty cycle balance module further arranged such that when Dbl1=Dnor1 and Dbl2=Dnor2, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 14 (depends on 1)

The duty cycle balance module of claim 1, wherein said input block, said output block and said cycle-by-cycle limit module are implemented with an application specific integrated circuit (ASIC), a digital, analog, or hybrid electronic circuit, or software executed in memory or a processor.

### Claim 15

A switch mode power converter having a half bridge, full bridge or push-pull topology in which a transformer is driven to conduct current in a first direction during a first half-cycle by a first pulse-width modulated (PWM) signal and in a second direction during a second half-cycle by a second PWM signal to achieve a desired result, comprising:
a current limiting mechanism which senses a current in said converter and adjusts the duty cycles of at least one of said first and second PWM signals when said sensed current exceeds a predetermined limit threshold; and
a duty cycle balance module comprising:
an input block which receives first signals Dnor—1 and Dnor—2 representative of the duty cycles which would be used for said first and second PWM signals to achieve said desired result if said duty cycles were not modified by said current limiting mechanism, and second signals Dact—1 and Dact—2 representative of the duty cycles that are actually used for said first and second PWM signals; and
an output block which provides signals Dbl—1 and Dbl—2, said duty cycle balance module arranged such that Dbl—1 and Dbl—2 modify said second PWM signals Dact—1 and Dact—2 as needed in response to said received first and second PWM signals so as to dynamically balance the duty cycles used for said first and second PWM signals and thereby reduce the magnetic flux imbalance in said transformer that might otherwise arise.

### Claim 16 (depends on 15)

The switch mode power converter of claim 15, wherein said current limiting mechanism includes a cycle-by-cycle limit module which receives signals Dbl—1 and Dbl—2 which are equal to or derived from said first signals Dnor—1 and Dnor—2 and a signal representative of said sensed current as inputs, and which provides said second signals Dact—1 and Dact—2 as outputs, said cycle-by-cycle limit module arranged to terminate signal Dact—1 during said first half-cycle if said sensed current exceeds said predetermined limit threshold during said first half-cycle and to terminate signal Dact—2 during said second half-cycle if said sensed current exceeds said predetermined limit threshold during said second half-cycle.

### Claim 17 (depends on 16)

The switch mode power converter of claim 16, wherein the amount of duty cycle lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch Dmis is given by:
Dmis=|ΣDloss—1−ΣDloss—2|,
said duty cycle balance module arranged to provide an output Dbl—1 during said first half-cycle given by:
Dbl—1=Dnor—1−Dmis
and an output Dbl—2 during said second half-cycle given by:
Dbl—2=Dnor—2−Dmis,
said signals Dbl—2 and Dbl—2 provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged such that when Dbl—1≧Dnor—1 and Dbl—2≧Dnor—2, or Dmis=0, indicating that there is no duty cycle imbalance, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 18 (depends on 16)

The switch mode power converter of claim 16, wherein the amount of duty cycle lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch Dmis is given by:
Dmis=|ΣDloss—1−ΣDloss—2|,
said duty cycle balance module arranged such that, when said sensed current exceeds said predetermined limit threshold during said first or second half-cycles, a value Dini is set to the value of duty cycle Dact as adjusted during the half-cycle that the predetermined limit threshold was exceeded and a value k is set to 0, said duty cycle balance module arranged to provide outputs Dbl—1[k] and Dbl—2[k] given by:
Dbl—1[k]=Dbl—1[k−1]+Dinc and Dbl—2[k]=Dbl—2[k−1]+Dinc,
where Dbl—1[k] and Dbl—2[k] are the outputs of the duty cycle balance module during the current half-cycle, Dbl—1[k−1] and Dbl—2[k−1] are the outputs of the duty cycle balance module during the previous half-cycle, Dbl—1[0] and Dbl—2[0]=Dini, Dinc is a fixed or variable duty cycle increment value, and k is incremented by 1 every half-cycle, said signals Dbl—1[k] and Dbl—2[k] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged such that, when Dbl—1[k]≧Dnor—1[k] and Dbl—2[k]≧Dnor—2[k], or Dmis=0 indicating that there is no duty cycle imbalance, Dbl—1[k]=Dnor—1[k], Dbl—2[k]=Dnor—2[k], and said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 19 (depends on 16)

The switch mode power converter of claim 16, wherein the amount of duty cycle lost Dloss—1 by the action of said cycle-by-cycle limit module during the first half-cycle is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost Dloss—2 by the action of said cycle-by-cycle limit module during the second half-cycle is given by:
Dloss—2=Dnor—2−Dact—2,
and the total duty cycle mismatch Dmis is given by:
Dmis=|ΣDloss—1−ΣDloss—2|,
said duty cycle balance module arranged such that, when said sensed current exceeds said predetermined limit threshold during said first or second half-cycles, a value Dpre is set to the duty cycle Dact for the current half-cycle, and said duty cycle balance module provides outputs Dbl—1 and Dbl—2 in the next half-cycle given by:
Dbl—1=Dpre or Dbl—2=Dpre;
and when said sensed current does not exceed said predetermined limit threshold during the current half-cycle, said duty cycle balance module provides outputs Dbl—1 and Dbl—2 in the next half-cycle given by:
Dbl—1=Dnor—1 or Dbl—2=Dnor—2,
said signals Dbl—1 and Dbl—2 provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged such that, when Dbl—1=Dnor—1 and Dbl—2=Dnor—2, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold during said first or second half-cycles.

### Claim 20

A duty cycle balance module for a switch mode power converter which includes an electromagnetic component that is driven to conduct current in a first direction by a first signal having an associated on- and off-time during a switching cycle and a second signal having an associated on- and off-time during said switching cycle and in a second direction by a third signal having an associated on- and off-time during said switching cycle and a fourth signal having an associated on- and off-time during said switching cycle to achieve a desired result, said first, second, third and fourth signals having associated duty cycles respectively defined as the ratio of their respective ON times to the period of said switching cycle, and which further includes a current limiting mechanism which senses a current in said converter and adjusts the ON time or duty cycle of at least one of said first, second, third and fourth signals when said sensed current exceeds a predetermined limit threshold, said duty cycle balance module comprising:
an input block which receives signals Dnor—1, Dnor—2 representative of the duty cycles or ON times which would be used for said first and second signals, respectively, or for said second and first signals, respectively, and signals Dnor—3, Dnor—4 representative of the duty cycles or ON times which would be used for said third and fourth signals, respectively, or for said fourth and third signals, respectively, to achieve said desired result if said duty cycles or ON times were not modified by said current limiting mechanism, and which receives signals Dact—1, Dact—2 representative of the duty cycles or ON times that are actually used for said first and second signals, respectively, or used for said second and first signals, respectively, and signals Dact—3, Dact—4 representative of the duty cycles or ON times that are actually used for said third and fourth signals, respectively, or used for said fourth and third signals, respectively; and
an output block which provides output signals Dbl—1, Dbl—2, Dbl—3 and Dbl—4, said duty cycle balance module arranged such that Dbl—1, Dbl—2, Dbl—3, Dbl—4 modify said signals Dact—1, Dact—2, Dact—3, Dact—4 as needed in response to said received first, second third and fourth signals so as to dynamically balance the duty cycles used for said first, second, third and fourth signals and thereby reduce the magnetic flux imbalance in said electromagnetic component that might otherwise arise.

### Claim 21 (depends on 20)

The duty cycle balance module of claim 20, wherein said switch mode power converter has a full-bridge or 4-switch buck-boost topology and said electromagnetic component is a transformer.

### Claim 22 (depends on 20)

The duty cycle balance module of claim 20, wherein said electromagnetic component is a motor.

### Claim 23 (depends on 20)

The duty cycle balance module of claim 20, wherein said first, second third and fourth signals are pulse-width modulated (PWM) signals.

### Claim 24 (depends on 20)

The duty cycle balance module of claim 20, wherein said first, second third and fourth signals are pulse-frequency modulated (PFM) signals.

### Claim 25 (depends on 20)

The duty cycle balance module of claim 20, wherein at least one of said first, second, third and fourth signals is a fixed width signal.

### Claim 26 (depends on 20)

The duty cycle balance module of claim 20, wherein said current limiting mechanism includes a cycle-by-cycle limit module which receives signals Dbl—1, Dbl—2, Dbl—3 and Dbl—4 which are equal to or derived from said first signals Dnor—1, Dnor—2, Dnor—3 and Dnor—4 and a signal representative of said sensed current as inputs, and which provides said signals Dact—1, Dact—2, Dact—3 and Dact—4 as outputs, said cycle-by-cycle limit module arranged to terminate at least one signal of Dact—1, Dact—2, Dact—3 and Dact—4 if said sensed current exceeds said predetermined limit threshold.

### Claim 27 (depends on 26)

The duty cycle balance module of claim 26, wherein the amount of duty cycle lost or ON time lost Dloss—1 by the action of said cycle-by-cycle limit module is given by:
Dloss—1=Dnor—1−Dact—1,
the amount of duty cycle lost or ON time lost Dloss—2 by the action of said cycle-by-cycle limit module is given by:
Dloss—2=Dnor—2−Dact—2,
the amount of duty cycle lost or ON time lost Dloss—3 by the action of said cycle-by-cycle limit module is given by:
Dloss—3=Dnor—3−Dact—3,
the amount of duty cycle lost or ON time lost Dloss4 by the action of said cycle-by-cycle limit module is given by:
Dloss—4=Dnor—4−Dact—4,
and the total duty cycle mismatches or ON time mismatches for every combination of two signals are given by:
Dmis—1=|ΣDloss—1−ΣDloss—3|,
Dmis—2=|ΣDloss—2−ΣDloss—4|.

### Claim 28 (depends on 27)

The duty cycle balance module of claim 27, arranged to provide an output Dbl—1 given by:
Dbl—1=Dnor—1−Dmis—1,
and an output Dbl—3 given by:
Dbl—3=Dnor—3−Dmis—1,
and an output Dbl—2 given by:
Dbl—2=Dnor—2−Dmis—2,
and an output Dbl—4 given by:
Dbl—4=Dnor—4−Dmis—2,
said signals Dbl—1, Dbl—2, Dbl—3 and Dbl—4 provided to said cycle-by-cycle limit module.

### Claim 29 (depends on 28)

The duty cycle balance module of claim 28, said duty cycle balance module further arranged such that when Dbl—1≧Dnor—1, Dbl—2≧Dnor—2, Dbl—3≧Dnor—3 and Dbl—4≧Dnor—4, or Dmis—1=0 and Dmis—2=0, indicating that there is no duty cycle or ON time imbalance, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold.

### Claim 30 (depends on 27)

The duty cycle balance module of claim 27, arranged such that, when said sensed current exceeds said predetermined limit threshold, a value Dini—1 is set to the value of the duty cycle or ON time Dact—1 as adjusted when the predetermined limit threshold was exceeded and a value m is set to 0, and a value Dini—2 is set to the value of the duty cycle or ON time Dact—2 as adjusted when the predetermined limit threshold was exceeded and a value n is set to 0.

### Claim 31 (depends on 30)

The duty cycle balance module of claim 30, arranged to provide an output Dbl—1[m] given by:
Dbl—1[m]=Dbl—3[m−1]+Dinc—1,
where Dbl—1 [m] is the output of the duty cycle balance module for said first signal or said second signal during the current switching cycle, Dbl—3[m−1] is the output of the duty cycle balance module for said third signal or said fourth signal during the previous switching cycle, Dinc—1 is a fixed or variable duty cycle or ON time increment value, and m is incremented by 1 every switching cycle, said signals Dbl—1[m] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—3 [m] given by:
Dbl—3[m]=Dbl—1[m]+Dinc—3,
where Dbl—3[m] is the output of the duty cycle balance module for said third signal or said fourth signal during the current switching cycle, Dbl—1[0]=Dini—1, Dinc—3 is a fixed or variable duty cycle or ON time increment value, and m is incremented by 1 every switching cycle, said signal Dbl—3[m] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—2[n] given by:
Dbl—2[n]=Dbl—4[n−1]+Dinc—2,
where Dbl—2[n] is the output of the duty cycle balance module for said second signal or said first signal during the current switching cycle, Dbl—4[n−1] is the output of the duty cycle balance module for said fourth signal or said third signal during the previous switching cycle, Dinc—2 is a fixed or variable duty cycle or ON time increment value, and n is incremented by 1 every switching cycle, said signal Dbl—2[n] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—4[n] given by:
Dbl—4[n]=Dbl—2[n]+Dinc—4,
where Dbl—4[n] is the output of the duty cycle balance module for said fourth signal or said third signal during the current switching cycle, Dbl—2[n] is the output of the duty cycle balance module for said second signal or said first signal during the current switching cycle, Dbl—2[0]=Dini2, Dinc—4 is a fixed or variable duty cycle or ON time increment value, and n is incremented by 1 every switching cycle, said signal Dbl—4[n] provided to said cycle-by-cycle limit module.

### Claim 32 (depends on 31)

The duty cycle balance module of claim 31, said duty cycle balance module further arranged such that when Dbl—1[m]≧Dnor—1[m], Dbl—2[n]≧Dnor—2[n], Dbl—3[m]≧Dnor—3[m] and Dbl—4[n]≧Dnor—4[n], or Dmis—1=0 and Dmis—2=0, indicating that there is no duty cycle or ON time imbalance, Dbl—1[m]=Dnor—1[m], Dinc—1=0, Dbl—3[m]=Dnor—3[m], Dinc—3=0, Dbl—2[n]=Dnor—2[n], Dinc—2=0, Dbl—4[n]=Dnor—4[n], Dinc—4=0 and said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold.

### Claim 33 (depends on 27)

The duty cycle balance module of claim 27, arranged such that when said sensed current exceeds said predetermined limit threshold, a value Dini—3 is set to the value of duty cycle or ON time Dact—3 as adjusted when the predetermined limit threshold was exceeded and a value m is set to 0, and a value Dini—4 is set to the value of duty cycle or ON time Dact—4 as adjusted when that the predetermined limit threshold was exceeded and a value n is set to 0.

### Claim 34 (depends on 33)

The duty cycle balance module of claim 33, arranged to provide an output Dbl—1[m] given by:
Dbl—1[m]=Dbl—3[m−1]+Dinc—1,
where Dbl—1[m] is the output of the duty cycle balance module for said first signal or said second signal during the current switching cycle, Dbl—3[m−1] is the output of the duty cycle balance module for said third signal or said fourth signal during the previous switching cycle, Dbl—3[0]=Dini—3, Dinc—1 is a fixed or variable duty cycle or ON time increment value, and m is incremented by 1 every switching cycle, said signal Dbl—1[m] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—3 [m] given by:
Dbl—3[m]=Dbl—1[m]+Dinc—3,
where Dbl—3[m] is the output of the duty cycle balance module for said third signal or said fourth signal during the current switching cycle, Dbl—1[m] is the output of the duty cycle balance module for said first signal or said second signal during the current switching cycle, Dinc—3 is a fixed or variable duty cycle or ON time increment value, and m is incremented by 1 every switching cycle, said signal Dbl—3[m] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—2[n] given by:
Dbl—2[n]=Dbl—4[n−1]+Dinc—2,
where Dbl—2[n] is the output of the duty cycle balance module for said second signal or said first signal during the current switching cycle, Dbl—4[n−1] is the output of the duty cycle balance module for said fourth signal or said third signal during the previous switching cycle, Dbl—4[0]=Dini—4, Dinc—2 is a fixed or variable duty cycle or ON time increment value, and n is incremented by 1 every switching cycle, said signal Dbl—2[n] provided to said cycle-by-cycle limit module;
said duty cycle balance module further arranged to provide an output Dbl—4[n] given by:
Dbl—4[n]=Dbl—2[n]+Dinc—4,
where Dbl—4[n] is the output of the duty cycle balance module for said fourth signal or said third signal during the current switching cycle, Dbl—2[n] is the output of the duty cycle balance module for said second signal or said first signal during the current switching cycle, Dinc—4 is a fixed or variable duty cycle or ON time increment value, and n is incremented by 1 every switching cycle, said signal Dbl—4[n] provided to said cycle-by-cycle limit module.

### Claim 35 (depends on 34)

The duty cycle balance module of claim 34, said duty cycle balance module further arranged such that when Dbl—1[m]≧Dnor—1[m], Dbl—2[n]≧Dnor—2[n], Dbl—3[m]≧ Dnor—3[m] and Dbl—4[n]≧Dnor—4[n], or Dmis—1=0 and Dmis—2=0, indicating that there is no duty cycle or ON time imbalance, Dbl—1[m]=Dnor—1[m], Dinc—1=0, Dbl—4[n]=Dnor—4[n], Dinc—4=0, Dbl—2[n]=Dnor—2[n], Dinc—2=0, Dbl—3[m]=Dnor—3[m], Dinc—3=0 and said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold.

### Claim 36 (depends on 20)

The duty cycle balance module of claim 20, arranged such that when said sensed current exceeds said predetermined limit threshold, a value Dpre1 is set to the value of the duty cycle or ON time Dact—1 as adjusted when the predetermined limit threshold was exceeded and said duty cycle balance module provides an output Dbl—3 during the current switching cycle given by:
Dbl—3=Dpre—1;
a value Dpre—2 is set to the value of the duty cycle or ON time Dact—2 as adjusted when the predetermined limit threshold was exceeded and said duty cycle balance module provides an output Dbl—4 during the current switching cycle given by:
Dbl—4=Dpre—2;
and when said sensed current does not exceed said predetermined limit threshold during the current switching cycle, said duty cycle balance module provides an output Dbl—3 during the current switching cycle given by:
Dbl—3=Dnor—3; and
said duty cycle balance module provides an output Dbl—4 during the current switching cycle given by:
Dbl—4=Dnor—4;
said signals Dbl—3 and Dbl—4 provided to said cycle-by-cycle limit module.

### Claim 37 (depends on 36)

The duty cycle balance module of claim 36, said duty cycle balance module further arranged such that when Dbl1=Dnor1, Dbl2=Dnor2, Dbl3=Dnor3, and Dbl4=Dnor4, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold.

### Claim 38 (depends on 20)

The duty cycle balance module of claim 20, arranged such that when said sensed current exceeds said predetermined limit threshold, a value Dpre3 is set to the value of the duty cycle or ON time Dact—3 as adjusted when the predetermined limit threshold was exceeded and said duty cycle balance module provides an output Dbl—3 during the next switching cycle given by:
Dbl—1=Dpre—3;
a value Dpre—4 is set to the value of the duty cycle or ON time Wact—2 as adjusted when the predetermined limit threshold was exceeded and said duty cycle balance module provides an output Dbl—2 during the next switching cycle given by:
Dbl—2=Dpre—4;
and when said sensed current does not exceed said predetermined limit threshold during the current switching cycle, said duty cycle balance module provides an output Dbl—1 during the next switching cycle given by:
Dbl—1=Dnor—1; and
said duty cycle balance module provides an output Dbl—2 during the next switching cycle given by:
Dbl—2=Dnor—2;
said signals Dbl—2 and Dbl—1 provided to said cycle-by-cycle limit module.

### Claim 39 (depends on 38)

The duty cycle balance module of claim 38, said duty cycle balance module further arranged such that when Dbl1=Dnor1, Dbl2=Dnor2, Dbl3=Dnor3, and Dbl4=Dnor4, said duty cycle balance module is bypassed or de-activated until said sensed current again exceeds said predetermined limit threshold.

### Claim 40 (depends on 20)

The duty cycle balance module of claim 20, wherein said input block, said output block and said cycle-by-cycle limit module are implemented with an application specific integrated circuit (ASIC), a digital, analog, or hybrid electronic circuit, or software executed in memory or a processor.