# US 2014/0192498 A1 · Direct metalization of electrical circuit structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0192498 A1 - Document ID: US20140192498A1 - Status: Published application - Kind: A1 - Application number: 14/238,638 - Filed: 2012-09-06 - Published: 2014-07-10 - Earliest claimed: 2011-09-08 - Assignees: Hsio Technologies, LLC - Inventors: James Rathburn - Web page: https://patentgrep.com/patent/US20140192498A1 ## CPC - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 3/4688: {Composite multilayer circuits, i.e. comprising insulating layers having different properties (having a special base or central core H05K3/4602)} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y10T 29/49117: Conductor or circuit manufacturing - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures. ## Claims ### Claim 1 An electrical interconnect comprising: a first circuitry layer comprising a first surface and a second surface; at least a first dielectric layer printed on the first surface of the first circuitry layer to include a plurality of first recesses; a conductive material plated on surfaces of a plurality of the first recesses comprising a first conductive structure electrically coupled to, and extending generally perpendicular to, the first circuitry layer; a filler material located in the first conductive structure; at least a second dielectric layer printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures; a conductive material plated on surfaces of a plurality of the second recesses comprising a second conductive structure electrically coupled to, and extending generally perpendicular to, the first conductive plating; and a filler material located in the second conductive structure. ### Claim 2 (depends on 1) The electrical interconnect of claim 1 comprising an IC device electrically coupled to a plurality of the second conductive structures. ### Claim 3 (depends on 1) The electrical interconnect of claim 1 comprising: a second circuitry layer located on the second dielectric layer and electrically coupled with a plurality of the second conductive structures; and at least a third dielectric layer printed on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive structures. ### Claim 4 (depends on 3) The electrical interconnect of claim 3 wherein portions of the second circuitry layer located in the third recesses etched away to expose a plurality of the second conductive structures. ### Claim 5 (depends on 3) The electrical interconnect of claim 3 comprising: a conductive material plated on surfaces of a plurality of the third recesses comprising a third conductive structure electrically coupled to, and extending parallel to the second conductive structures; and an IC device including a plurality of contact pads electrically coupled to a plurality of the third conductive structures, wherein the IC device is electrically coupled by one of a flip chip attachment directly to a plurality of third conductive structures, solder balls, or wire bonding. ### Claim 6 (depends on 3) The electrical interconnect of claim 3 comprising: a third circuitry layer located on the third dielectric layer; and a covering layer extending across the third circuitry layer, the covering layer comprising a plurality of openings exposing contact pads on the third circuitry layer configured to electrically couple with an IC device. ### Claim 7 (depends on 1) The electrical interconnect of claim 1 comprising a covering layer extending across the second surface of the first circuitry layer, the covering layer comprising a plurality of openings exposing a plurality of contact pads on the first circuitry layer adapted to electrically couple with a PCB. ### Claim 8 (depends on 1) The electrical interconnect of claim 1 comprising a dielectric material printed in one or more of the recesses to surround one or more conductive structure. ### Claim 9 (depends on 1) The electrical interconnect of claim 1 wherein the conductive material comprises one of sintered conductive particles or a conductive ink. ### Claim 10 (depends on 1) The electrical interconnect of claim 1 comprising at least one printed electrical device located on one of the dielectric layers and electrically coupled to at least a portion of the circuitry layers. ### Claim 11 (depends on 1) The electrical interconnect of claim 1 wherein the filler material is one of a conductive or a non-conductive material. ### Claim 12 A method of making an electrical interconnect comprising the steps of: providing a first circuitry layer comprising a first surface and a second surface; printing at least a first dielectric layer on the first surface of the first circuitry layer to include a plurality of first recesses; depositing a conductive material on surfaces of a plurality of the first recesses comprising a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer; printing a filler material in the first conductive structure; printing at least a second dielectric layer on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures; and depositing a conductive material on surfaces of a plurality of the second recesses comprising a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures. ### Claim 13 (depends on 12) The method of claim 12 comprising electrically coupling contact pads on an IC device to a plurality of the second conductive structures. ### Claim 14 (depends on 12) The method of claim 12 comprising the steps of: locating a second circuitry layer on the second dielectric layer to electrically couple the second circuitry layer with a plurality of the second conductive structures; and printing at least a third dielectric layer on the second dielectric layer to include a plurality of third recesses generally aligned with a plurality of the second conductive structures. ### Claim 15 (depends on 14) The method of claim 14 comprising etching away portions of the second circuitry layer located in the third recesses to expose a plurality of the second conductive structures. ### Claim 16 (depends on 14) The method of claim 14 comprising the steps of: plating a conductive material on surfaces of a plurality of the third recesses comprising a plurality of third conductive structure electrically coupled to, and extending parallel to the second conductive structures; and electrically coupling contact pads on an IC device to a plurality of the third conductive structures, wherein the step of electrically coupling comprises one of a flip chip attachment directly to a plurality of third conductive structures, solder balls, or wire bonding. ### Claim 17 (depends on 14) The method of claim 14 comprising the steps of: locating a third circuitry layer on the third dielectric layer; and attaching a covering layer to the third circuitry layer, the covering layer comprising a plurality of openings exposing contact pads on the third circuitry layer configured to electrically couple with an IC device. ### Claim 18 (depends on 12) The method of claim 12 comprising attaching a covering layer to the second surface of the first circuitry layer, the covering layer comprising a plurality of openings exposing a plurality of contact pads on the first circuitry layer adapted to electrically couple with a PCB. ### Claim 19 (depends on 12) The method of claim 12 comprising printing a dielectric material in one or more of the recesses to surround one or more of the conductive structures. ### Claim 20 (depends on 12) The method of claim 12 comprising printing at least one electrical device on one of the dielectric layers and electrically coupling the electrical device to at least a portion of the circuitry layers.