# US 2014/0192491 A1 · Circuit substrate structure and method for manufacturing thereof

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- Number: US 2014/0192491 A1
- Document ID: US20140192491A1
- Status: Published application
- Kind: A1
- Application number: 14/144,599
- Filed: 2013-12-31
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: E Ink Holdings Inc.
- Applicants: E Ink Holdings Inc.
- Inventors: Ming-Sheng CHIANG; Chi-Ming WU; Chen-Yuan SUNG; Chen-Lung LO; Ta-Nien LUAN
- Web page: https://patentgrep.com/patent/US20140192491A1

## CPC

- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)}
- H05K 3/32: electrically connecting electric components or wires to printed circuits
- G02F 1/13452: {Conductors connecting driver circuitry and terminals of panels}
- H05K 3/281: {by means of a preformed insulating foil (H05K3/284 takes precedence)}
- H05K 3/284: {for encapsulating mounted components (H05K1/185 takes precedence)}
- H05K 3/361: {Assembling flexible printed circuits with other printed circuits}
- H05K 2201/10128: Display
- H05K 2203/063: of preperforated insulating layer
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The invention provides a circuit substrate structure and a method for manufacturing thereof. The circuit substrate structure includes a substrate, a pixel array layer, a display unit, a peripheral circuit layer, at least one integrated circuit chip, a flexible printed circuit board, at least one flattening material layer and a passivation layer. In the circuit substrate structure, the flattening material layer is positioned on the peripheral circuit layer, and possesses at least one opening corresponded to and around the integrated circuit chip. By positioning the flattening material layer, the circuit substrate structure possesses a flat surface, and prevents producing air bubbles, so as to enhance the reliability of the display device.

## Claims

### Claim 1

A circuit substrate structure, comprising:
a substrate having a display area and a non-display area;
a pixel array layer positioned on the display area of the substrate;
a display unit positioned on the pixel array layer;
a peripheral circuit layer positioned on the nondispiay area of the substrate, and electrically connected to the pixel array layer;
at least one integrated circuit chip positioned on the peripheral circuit layer, and electrically connected to the pixel array layer;
a flexible printed circuit board positioned on the peripheral circuit layer, and electrically connected to the integrated circuit chip, the pixel array layer or the combinations thereof;
at least one flattening material layer positioned on the peripheral circuit layer, and covering a portion of the flexible printed circuit board, the flattening material layer having at least one opening which corresponds to and surrounds the integrated circuit chip; and
a passivation layer positioned on and covering the display unit and the flattening material layer.

### Claim 2 (depends on 1)

The circuit substrate structure of claim 1, further comprising a sealant positioned between the display unit and the flattening material layer.

### Claim 3 (depends on 2)

The circuit substrate structure of claim 2, wherein the sealant is positioned in the opening of the flattening material layer.

### Claim 4 (depends on 2)

The circuit substrate structure of claim 2, wherein the sealant is heat curing adhesive, optical light-sensitive adhesive or after-light-sensitive heat curing adhesive.

### Claim 5 (depends on 1)

The circuit substrate structure of claim 1, wherein the flattening material layer overs more than 50% of the non-display area of the substrate.

### Claim 6 (depends on 1)

The circuit substrate structure of claim 1, wherein the material of the substrate comprises glass, hard plastic or flexible plastic.

### Claim 7 (depends on 1)

The circuit substrate structure of claim 1, wherein the peripheral circuit layer comprises a thin-film transistor layer or a conductive circuit layer.

### Claim 8 (depends on 1)

The circuit substrate structure of claim 1, wherein the coefficient of linear thermal expansion of the flattening material layer is less than 70×10−6/K.

### Claim 9 (depends on 1)

The circuit substrate structure of claim 1, wherein the flattening material layer comprises glass, polyethylene terephthalate (PET), polyethylene naphthalene dicarboxylate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polystyrene (PS), or the combinations thereof.

### Claim 10 (depends on 1)

The circuit substrate structure of claim 1, wherein the thickness of the flattening material layer is the same as the thickness of the display unit.

### Claim 11 (depends on 1)

The circuit substrate structure of claim 1, wherein the thickness of the flattening material layer is larger than or equal to the integrated circuit chip.

### Claim 12

A method of manufacturing a circuit substrate structure used to a display, comprising the steps of:
providing a substrate having a display area and a non-display area,
forming a pixel array layer on the display area of the substrate,
forming a display unit on the pixel array layer,
forming a peripheral circuit layer on the non-display area, wherein the peripheral circuit layer is electrically connected to the pixel array layer,
forming at least one integrated circuit chip on the peripheral circuit layer, wherein the integrated circuit chip is electrically connected to the pixel array layer,
forming a flexible printed circuit board on the peripheral circuit layer, wherein the flexible printed circuit board is electrically connected to the integrated circuit chip, the pixel array layer or the combinations thereof,
forming at least one flattening material layer on the peripheral circuit layer and covering a portion of the flexible printed circuit board, wherein the flattening material layer has at least one opening corresponding to and surrounding the integrated circuit chip; and
forming a passivation layer on the display unit and the flattening material layer.

### Claim 13 (depends on 12)

The method of claim 12, before the step of forming the passivation layer, further comprising the step of forming a sealant between the display unit and the flattening material layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the sealant is positioned in the opening of the flattening material layer,

### Claim 15 (depends on 12)

The method of claim 12, wherein the flattening material layer covers more than 50% of the non-display area of the substrate.