# US 2014/0192069 A1 · Apparatus and method for memory-hierarchy aware producer-consumer instruction

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- Number: US 2014/0192069 A1
- Document ID: US20140192069A1
- Status: Published application
- Kind: A1
- Application number: 13/994,122
- Filed: 2011-12-21
- Published: 2014-07-10
- Earliest claimed: 2011-12-21
- Assignees: Intel Corporation
- Inventors: Shlomo Raikin; Raanan Sade; Robert Valentine; Julius Yuli Mandelblat; Ron Shalev; Larisa Novakovsky
- Web page: https://patentgrep.com/patent/US20140192069A1

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30087: {Synchronisation or serialisation instructions}
- G06F 9/3881: {Arrangements for communication of instructions and data}
- G06F 13/1673: {using buffers}
- G06F 13/38: Information transfer, e.g. on bus (G06F13/14 takes precedence)
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T 1/60: Memory management
- G06F 12/0866: for peripheral storage systems, e.g. disk cache
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

## Claims

### Claim 1

A method for transferring a chunk of data from a core of a central processing unit (CPU) to a graphics processing unit (GPU), comprising:
writing data to a buffer within the core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU;
setting an indication to indicate to the GPU that data is available in the cache; and
upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

### Claim 2 (depends on 1)

The method as in claim 1 wherein the indication comprises a flag writable by the core and readable by the GPU.

### Claim 3 (depends on 2)

The method as in claim 2 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

### Claim 4 (depends on 1)

The method as in claim 1 wherein the GPU reads the indication via a polling technique in which the GPU periodically reads polls for the indication.

### Claim 5 (depends on 1)

The method as in claim 1 wherein the GPU reads the indication in response to an interrupt signal.

### Claim 6 (depends on 1)

The method as in claim 1 wherein the operations of the method are executed by the core in response to the execution of a first instruction by the core.

### Claim 7 (depends on 6)

The method as in claim 6 wherein the first instruction comprises a MovNonAllocate store instruction.

### Claim 8 (depends on 6)

The method as in claim 6 further comprising:
permitting the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

### Claim 9 (depends on 8)

The method as in claim 8 further comprising:
permitting the first instruction to be interleaved with a plurality of other instructions of different instruction types.

### Claim 10 (depends on 9)

The method as in claim 9 wherein the other instructions are write-back store instructions and the first instruction is a MovNonAllocate store instruction.

### Claim 11 (depends on 1)

The method as in claim 1 wherein the buffer within the CPU is a write-back buffer and wherein the cache accessible by both the core and the GPU is a level 3 (L3) cache.

### Claim 12 (depends on 1)

The method as in claim 1 wherein the CPU comprises a plurality of cores, each capable of performing the method.

### Claim 13

An instruction processing apparatus comprising:
at least one core and a cache accessible by both the core and a GPU;
CPU-GPU producer-consumer logic configured to perform the operations of:
writing data to a buffer within the core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; and
setting an indication to indicate to the GPU that data is available in the cache;
wherein upon the GPU detecting the indication, the data is provided to the GPU from the cache upon receipt of a read signal from the GPU.

### Claim 14 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the indication comprises a flag writable by the core and readable by the GPU.

### Claim 15 (depends on 14)

The instruction processing apparatus as in claim 14 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

### Claim 16 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the GPU reads the indication via a polling technique in which the GPU periodically reads polls for the indication.

### Claim 17 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the GPU reads the indication in response to an interrupt signal.

### Claim 18 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the operations of the instruction processing apparatus are executed by the core in response to the execution of a first instruction by the core.

### Claim 19 (depends on 18)

The instruction processing apparatus as in claim 18 wherein the first instruction comprises a MovNonAllocate store instruction.

### Claim 20 (depends on 18)

The instruction processing apparatus as in claim 18 wherein the CPU-GPU producer-consumer logic permits the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

### Claim 21 (depends on 20)

The instruction processing apparatus as in claim 20 wherein the CPU-GPU producer-consumer logic permits the first instruction to be interleaved with a plurality of other instructions of different instruction types.

### Claim 22 (depends on 21)

The instruction processing apparatus as in claim 21 wherein the other instructions are write-back store instructions and the first instruction is a MovNonAllocate store instruction.

### Claim 23 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the buffer within the CPU is a write-back buffer and wherein the cache accessible by both the core and the GPU is a level 3 (L3) cache.

### Claim 24 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the CPU comprises a plurality of cores, each having CPU-GPU producer-consumer logic for performing the specified operations.

### Claim 25

A computer system comprising:
a graphics processor unit (GPU) for processing a set of graphics instructions to render video; and
a central processing unit comprising:
at least one core and a cache accessible by both the core and the GPU;
CPU-GPU producer-consumer logic configured to perform the operations of:
writing data to a buffer within the core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; and
setting an indication to indicate to the GPU that data is available in the cache;
wherein upon the GPU detecting the indication, the data is provided to the GPU from the cache upon receipt of a read signal from the GPU.