# US 2014/0191936 A1 · Driving Module and Driving Method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191936 A1 - Document ID: US20140191936A1 - Status: Published application - Kind: A1 - Application number: 13/934,247 - Filed: 2013-07-03 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Novatek Microelectronics Corp. - Applicants: NOVATEK Microelectronics Corp. - Inventors: Hsi-Chi Ho; Jen-Hao Liao; Yu-Kuang Chang - Web page: https://patentgrep.com/patent/US20140191936A1 ## CPC - G09G 3/3406: {Control of illumination source (illumination devices structurally associated with liquid crystal cells G02F1/1336)} - G09G 2310/0237: Switching ON and OFF the backlight within one frame - G09G 2320/0626: for control of overall brightness - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A driving module for a liquid crystal display device is disclosed. The driving module includes a data line signal processing unit, for generating a plurality of data driving signals, a scan line signal processing unit, for generating a plurality of gate driving signals, and a control unit, for generating a display clock, to control the data line signal processing unit and the scan line signal processing unit to address a plurality of pixels of the liquid crystal display device according to the display clock. The display clock is a normal operating clock under a normal operating mode and is a blanking backlight clock under a blanking backlight mode, wherein a frequency of the normal operating clock is less than a frequency of the blanking backlight clock. ## Claims ### Claim 1 A driving module for a liquid crystal display device, comprising: a data line signal processing unit, for generating a plurality of data driving signals; a scan line signal processing unit, for generating a plurality of gate driving signals; and a control unit, for generating a display clock, to control the data line signal processing unit and the scan line signal processing unit to address a plurality of pixels of the liquid crystal display device according to the display clock; wherein the display clock is a normal operating clock under a normal operating mode and is a blanking backlight (BBL) clock under a blanking backlight mode, wherein a frequency of the normal operating clock is less than a frequency of the blanking backlight clock. ### Claim 2 (depends on 1) The driving module of claim 1, wherein the driving module performs addressing by a first addressing capability under the normal operating mode, and performs addressing by a second addressing capability under the blanking backlight mode, and the second addressing capability is stronger than the first addressing capability. ### Claim 3 (depends on 2) The driving module of claim 2, wherein the driving module switches at least one setting value of a DC-DC converter driving capability, a boost ratio, a boost type, a digital core voltage and a source operational amplifier (SOP) driving capability between a first setting value and a second value, to switch between the first addressing capability and the second addressing capability. ### Claim 4 (depends on 1) The driving module of claim 1 further comprising a frequency dividing circuit, for dividing a frequency of the blanking backlight clock to generate the normal operating clock. ### Claim 5 (depends on 1) The driving module of claim 1, wherein the control unit delays a synchronization signal for a specific time under the blanking backlight mode, to generate a delayed synchronization signal for a non-overlapping control over an on-time of a backlight and an addressing time of the data line signal processing unit and the scan line signal processing unit according to the blanking backlight clock. ### Claim 6 A driving method for a liquid crystal display device, comprising: generating a display clock; and generating a plurality of data driving signals and a plurality of gate driving signals to address a plurality of pixels of the liquid crystal display device according to the display clock; wherein the display clock is a normal operating clock under a normal operating mode and is a blanking backlight (BBL) clock under a blanking backlight mode, wherein a frequency of the normal operating clock is less than a frequency of the blanking backlight clock. ### Claim 7 (depends on 6) The driving method of claim 6 further comprising: performing addressing by a first addressing capability under the normal operating mode, and performing addressing by a second addressing capability under the blanking backlight mode, and the second addressing capability is stronger than the first addressing capability. ### Claim 8 (depends on 7) The driving method of claim 7 further comprising: switching at least one setting value of a DC-DC converter driving capability, a boost ratio, a boost type, a digital core voltage and a source operational amplifier (SOP) driving capability between a first setting value and a second value, to switch between the first addressing capability and the second addressing capability. ### Claim 9 (depends on 6) The driving method of claim 6 further comprising: dividing a frequency of the blanking backlight clock to generate the normal operating clock. ### Claim 10 (depends on 6) The driving method of claim 6 further comprising: delaying a synchronization signal for a specific time under the blanking backlight mode, to generate a delayed synchronization signal for a non-overlapping control over an on-time of a backlight and an addressing time of the data line signal processing unit and the scan line signal processing unit according to the blanking backlight clock.