# US 2014/0191934 A1 · Driving circuit of a semiconductor display device and the semiconductor display device

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- Number: US 2014/0191934 A1
- Document ID: US20140191934A1
- Status: Published application
- Kind: A1
- Application number: 14/153,667
- Filed: 2014-01-13
- Published: 2014-07-10
- Earliest claimed: 1998-03-27
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Jun KOYAMA; Shunpei YAMAZAKI
- Web page: https://patentgrep.com/patent/US20140191934A1

## CPC

- G09G 3/3674: {Details of drivers for scan electrodes}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3611: {Control of matrices with row and column drivers}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3688: {suitable for active matrices only}
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

There are provided a driving circuit of a semiconductor display device which can obtain an excellent picture without picture blur (display unevenness) and with high fineness/high resolution, and the semiconductor display device. A buffer circuit used in the driving circuit of the semiconductor display device is constituted by a plurality of TFTs each having a small channel width, and a plurality of such buffer circuits are connected in parallel with each other.

## Claims

### Claim 1

(canceled)

### Claim 2

A display device, comprising:
a gate signal line side driving circuit including a shift register circuit,
wherein the gate signal line side driving circuit includes a buffer circuit electrically connected with the shift register circuit, the buffer circuit including a plurality of inverters,
wherein at least one of the plurality of inverters comprises a plurality of n-channel thin film transistors and at least one p-channel thin film transistor, and
wherein each of the plurality of n-channel thin film transistors is connected in parallel with each other.

### Claim 3 (depends on 2)

The display device according to claim 2, wherein the display device has an electroluminescence element.

### Claim 4 (depends on 2)

The display device according to claim 2, wherein each of the plurality of n-channel thin film transistors has a plurality of gate electrodes.

### Claim 5 (depends on 2)

The display device according to claim 2, wherein the p-channel thin film transistor has a plurality of gate electrodes.

### Claim 6 (depends on 2)

The display device according to claim 2, wherein the plurality of n-channel thin film transistors have channel widths of 100 μm or less.

### Claim 7

A display device, comprising:
a gate signal line side driving circuit including a shift register circuit,
wherein the gate signal line side driving circuit includes a buffer circuit electrically connected with the shift register circuit, the buffer circuit including a plurality of inverters,
wherein at least one of the plurality of inverters comprises a plurality of p-channel thin film transistors and at least one n-channel thin film transistor, and
wherein each of the plurality of p-channel thin film transistors is connected in parallel with each other.

### Claim 8 (depends on 7)

The display device according to claim 7, wherein the display device has an electroluminescence element.

### Claim 9 (depends on 7)

The display device according to claim 7, wherein each of the plurality of p-channel thin film transistors has a plurality of gate electrodes.

### Claim 10 (depends on 7)

The display device according to claim 7, wherein the n-channel thin film transistor has a plurality of gate electrodes.

### Claim 11 (depends on 7)

The display device according to claim 7, wherein the plurality of p-channel thin film transistors have channel widths of 100 μm or less.

### Claim 12

A display device, comprising:
a pixel matrix circuit; and
a first gate signal line side driving circuit and a second gate signal line side driver circuit, wherein the pixel matrix circuit is located between the first gate signal line side driving circuit and the second gate signal line side driver circuit, each of the first gate signal line side driving circuit and the second gate signal line side driver circuit including a shift register circuit and a buffer circuit electrically connected with the shift register circuit, the buffer circuit comprising an inverter,
wherein the inverter comprises a plurality of n-channel thin film transistors and at least one p-channel thin film transistor,
wherein each of the plurality of n-channel thin film transistors is connected in parallel with each other, and
wherein a channel region of the plurality of n-channel thin film transistors comprises crystalline silicon.

### Claim 13 (depends on 12)

The display device according to claim 12, wherein the display device has an electroluminescence element.

### Claim 14 (depends on 12)

The display device according to claim 12, wherein each of the plurality of n-channel thin film transistors has a plurality of gate electrodes.

### Claim 15 (depends on 12)

The display device according to claim 12, wherein the plurality of n-channel thin film transistors share a first semiconductor film for a channel region thereof.

### Claim 16 (depends on 12)

The display device according to claim 12, wherein the display device is a liquid crystal display device.

### Claim 17 (depends on 12)

The display device according to claim 12, wherein the plurality of n-channel thin film transistors have channel widths of 100 μm or less.

### Claim 18

A display device, comprising:
a pixel matrix circuit; and
a first gate signal line side driving circuit and a second gate signal line side driver circuit, wherein the pixel matrix circuit is located between the first gate signal line side driving circuit and the second gate signal line side driver circuit, each of the first gate signal line side driving circuit and the second gate signal line side driver circuit including a shift register circuit and a buffer circuit electrically connected with the shift register circuit, the buffer circuit comprising an inverter,
wherein the inverter comprises a plurality of p-channel thin film transistors and at least one n-channel thin film transistor,
wherein each of the plurality of p-channel thin film transistors is connected in parallel with each other, and
wherein a channel region of the plurality of p-channel thin film transistors comprises crystalline silicon.

### Claim 19 (depends on 18)

The display device according to claim 18, wherein the display device has an electroluminescence element.

### Claim 20 (depends on 18)

The display device according to claim 18, wherein each of the plurality of p-channel thin film transistors has a plurality of gate electrodes.

### Claim 21 (depends on 18)

The display device according to claim 18, wherein the plurality of p-channel thin film transistors share a first semiconductor film for a channel region thereof.

### Claim 22 (depends on 18)

The display device according to claim 18, wherein the display device is a liquid crystal display device.

### Claim 23 (depends on 18)

The display device according to claim 18, wherein the plurality of p-channel thin film transistors have channel widths of 100 μm or less.
