# US 2014/0191891 A1 · Analogue-to-digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191891 A1 - Document ID: US20140191891A1 - Status: Published application - Kind: A1 - Application number: 14/209,496 - Filed: 2014-03-13 - Published: 2014-07-10 - Earliest claimed: 2011-02-14 - Assignees: Nordic Semiconductor ASA - Applicants: Nordic Semiconductor Asa - Inventors: Carsten Wulff; Ola Bruset; Werner Luzi - Web page: https://patentgrep.com/patent/US20140191891A1 ## CPC - H03M 3/39: {Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004)} - H03M 3/38: {Calibration} - H03M 3/43: {the quantiser being a single bit one} - H03M 3/456: {the modulator having a first order loop filter in the feedforward path} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input. ## Claims ### Claim 1 An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter having a single-ended analogue input, a converter reference input, and a ground connection, wherein the converter comprises: a resistor-capacitor integrator arranged to receive the single-ended analogue input, wherein the integrator comprises a differential amplifier having an amplifier reference input; a clocked comparator arranged to receive an output from the integrator and having a comparator reference input; and circuitry arranged so that the amplifier reference input and the comparator reference input can be maintained at a common voltage derived from the converter reference input. ### Claim 2 (depends on 1) An analogue-to-digital converter as claimed in claim 1, wherein the resistor-capacitor integrator comprises a single capacitor. ### Claim 3 (depends on 1, 2) An analogue-to-digital converter as claimed in claim 1 or 2, wherein the said common voltage is half of the converter reference input voltage. ### Claim 4 An analogue-to-digital converter as claimed in any preceding claim, wherein said circuitry comprises a voltage divider between the converter reference input and ground, the output of which is connected to the amplifier reference input and to the comparator reference input. ### Claim 5 (depends on 4) An analogue-to-digital converter as claimed in claim 4, wherein the voltage divider comprises two equal resistors. ### Claim 6 An analogue-to-digital converter as claimed in any preceding claim, wherein the amplifier reference input is a non-inverting input to the differential amplifier. ### Claim 7 An analogue-to-digital converter as claimed in any preceding claim, wherein the differential amplifier is an operational transconductance amplifier. ### Claim 8 An analogue-to-digital converter as claimed in any preceding claim, wherein the converter comprises circuitry arranged so that, in use, the current flowing into a second input to the amplifier depends on: (i) the voltage at the single-ended analogue input, (ii) the converter reference voltage, and (iii) the output state of the clocked comparator. ### Claim 9 (depends on 8) An analogue-to-digital converter as claimed in claim 8, wherein said second input to the amplifier is an inverting input. ### Claim 10 An analogue-to-digital converter as claimed in any preceding claim, further comprising a clock input, wherein the comparator is configured to use the clock input to define an integration step. ### Claim 11 An analogue-to-digital converter as claimed in any preceding claim, wherein said circuitry comprises means arranged to switch the voltage at a point in the circuitry between two values in dependence on the binary output of the comparator. ### Claim 12 (depends on 11) An analogue-to-digital converter as claimed in claim 11, wherein a first of said two values is ground and a second of said two values is the converter reference voltage. ### Claim 13 An analogue-to-digital converter as claimed in any preceding claim, wherein said circuitry comprises an arrangement of first, second and third resistors, wherein a first end of the first resistor is connected to the single-ended analogue input, a first end of the second resistor is connected to ground, and a first end of the third resistor is switchably connectable to the converter reference input or to ground. ### Claim 14 (depends on 13) An analogue-to-digital converter as claimed in claim 13, wherein the second ends of the three resistors are each connected to a second input to the amplifier. ### Claim 15 (depends on 13, 14) An analogue-to-digital converter as claimed in claim 13 or 14, wherein the circuitry is arranged such that the switching of the voltage at the first end of the third resistor is controlled in dependence on the binary output of the comparator. ### Claim 16 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12) An analogue-to-digital converter as claimed in any of claims 1 to 12, wherein said circuitry comprises an arrangement of first, second, third and fourth resistors, wherein a first end of the first resistor is connected to the single-ended analogue input, a first end of the second resistor is connected to ground, a first end of the third resistor is connected to ground, and a first end of the fourth resistor is connected to the converter reference input or to ground. ### Claim 17 (depends on 16) An analogue-to-digital converter as claimed in claim 16, wherein the second ends of the third resistor and the fourth resistor are switchably connectable to a second input to the amplifier such that either one or other of the second ends is connected at a time, and wherein the second ends of the first resistor and second resistor are connected to the second input to the amplifier. ### Claim 18 (depends on 17) An analogue-to-digital converter as claimed in claim 17, wherein the circuitry is arranged such that said switching between the third resistor and the fourth resistor is controlled in dependence on the binary output of the comparator. ### Claim 19 (depends on 17, 18) An analogue-to-digital converter as claimed in claim 17 or 18, wherein the third and fourth resistors have the same nominal value. ### Claim 20 (depends on 13, 14, 15, 16, 17, 18, 19) An analogue-to-digital converter as claimed in any of claims 13 to 19, wherein the first and second resistors are variable, and the converter comprises means for receiving an input representative of a desired gain or mid-scale, and for adjusting the first and second resistors so that the converter provides the desired gain or mid-scale. ### Claim 21 (depends on 13, 14, 15, 16, 17, 18, 19, 20) An analogue-to-digital converter as claimed in any of claims 13 to 20, wherein the gain or mid-scale of the converter is a function of (i) the ratio of the value of the first resistor to the value of said resistor connected or connectable to the converter reference input or to ground; and (ii) the ratio of the value of the second resistor value to the value of said resistor connected or connectable to the converter reference input or to ground. ### Claim 22 An analogue-to-digital converter as claimed in any preceding claim, comprising a counter arranged to receive the binary output of the comparator. ### Claim 23 (depends on 22) An analogue-to-digital converter as claimed in claim 22, wherein the counter is arranged to receive a clock signal and to count for how many clock cycles the output of the comparator is high, or to count for how many clock cycles the output of the comparator is low, over a time period, and wherein the converter is arranged so that the counter and the comparator receive the same clock signal. ### Claim 24 An analogue-to-digital converter as claimed in any preceding claim, wherein the converter is an incremental converter. ### Claim 25 An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter having a single-ended analogue input, a converter reference input, and a ground connection, wherein the converter comprises an input resistor having a first end connected to the single-ended analogue input, and an offset resistor having a first end connected to ground, wherein the second ends of the input and offset resistors are connected to an input to a differential amplifier in an RC integrator circuit, wherein the input to the differential amplifier is also selectably connectable through a reference resistor to either the converter reference input or to ground, and wherein the gain of the converter is determined as a function of the ratio of the input resistor value to the reference resistor value and of the ratio of the offset resistor value to the reference resistor value. ### Claim 26 (depends on 25) An analogue-to-digital converter as claimed in claim 25, wherein a first end of the reference resistor is connected to switching means arranged to maintain the voltage at the first end of the reference resistor at either ground or a voltage at the converter reference input, with the second end of the reference resistor being connected to the differential amplifier input. ### Claim 27 (depends on 25) An analogue-to-digital converter as claimed in claim 25, comprising first and second reference resistors and configured to maintain a first end of the first reference resistor at ground and to maintain a first end of the second reference resistor at a voltage at the converter reference input, with the input to the differential amplifier being connected to switching means arranged to connect the input either to the second end of the first reference resistor or to the second end of the second reference resistor. ### Claim 28 (depends on 25, 26, 27) An analogue-to-digital converter as claimed in any of claims 25 to 27, wherein the mid-scale of the converter is determined as a further function of the ratio of the input resistor value to the reference resistor value and of the ratio of the offset resistor value to the reference resistor value. ### Claim 29 (depends on 25, 26, 27, 28) An analogue-to-digital converter as claimed in any of claims 25 to 28, comprising a clocked comparator arranged to receive an output from the integrator, and a counter arranged to receive the binary output of the comparator. ### Claim 30 (depends on 29) An analogue-to-digital converter as claimed in claim 29, wherein the counter is arranged to receive a clock signal and to count for how many clock cycles the output of the comparator is high, or to count for how many clock cycles the output of the comparator is low, over a time period, and wherein the converter is arranged so that the counter and the comparator receive the same clock signal. ### Claim 31 (depends on 25, 26, 27, 28, 29, 30) An analogue-to-digital converter as claimed in any of claims 25 to 30, wherein the converter is an incremental converter.