# US 2014/0191890 A1 · Apparatus, systems and methods for for digital testing of adc/dac combination > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191890 A1 - Document ID: US20140191890A1 - Status: Published application - Kind: A1 - Application number: 13/992,765 - Filed: 2011-12-07 - Published: 2014-07-10 - Earliest claimed: 2011-12-07 - Assignees: Intel Corporation - Inventors: Stephen J. Spinks; Andrew Talbot; Colin Mair - Web page: https://patentgrep.com/patent/US20140191890A1 ## CPC - H03M 1/1071: {Measuring or testing} - H03M 1/10: Calibration or testing - H03M 1/109: {for DC performance, i.e. static testing (H03M1/1085 takes precedence)} - H03M 1/46: with digital/analogue converter for supplying reference values to converter - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 1/365: {the voltage divider being a single resistor string} - H03M 1/765: {using a single level of switches which are controlled by unary decoded digital signals} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches. ## Claims ### Claim 1 A testing circuit comprising: a plurality of built-in test switches capable of coupling at least one tap voltage from a digital to analog converter (DAC) to a test bus and capable of providing an analog to digital converter (ADC) with a variable reference input voltage; a test pattern generator capable of generating a code pattern having a plurality of sequential values; and a test controller having an input terminal connected to the test bus, thereby receiving an output signal from the ADC and DAC resulting from application of the code pattern to the DAC and control of the plurality of built-in test switches; wherein the test controller is capable of configuring the plurality of built-in test switches between a test-mode operation and a normal-mode operation. ### Claim 2 (depends on 1) The testing circuit of claim 1, wherein the digital to analog converter comprises a plurality of resistors configured in a resistor string, a plurality of switches connected to the plurality of resistors, and decoder logic adapted to control the plurality of switches based on the code pattern to generate the at least one tap voltage. ### Claim 3 (depends on 2) The testing circuit of claim 2, wherein the analog to digital converter comprises a plurality of comparators to receive at least one tap voltage from the DAC and the variable reference input voltage. ### Claim 4 (depends on 3) The testing circuit of claim 3, wherein the test controller in the test-mode operation is capable of determining whether the digital to analog converter (DAC) or the analog to digital converter (ADC) is faulty. ### Claim 5 (depends on 4) The testing circuit of claim 4, wherein the test bus comprises an analog test bus and a digital test bus. ### Claim 6 (depends on 3) The testing circuit of claim 3, wherein the plurality of comparators can be tested by setting one of the at least one tap voltage to mid code using the generated code pattern and sweeping one of the at least one tap voltage through a series of values. ### Claim 7 (depends on 3) The testing circuit of claim 3, wherein the plurality of switches, decode logic, plurality of resistors can be tested sweeping the code pattern through a series of values and measuring the response of the ADC and the DAC at the analog test bus and the digital test bus ### Claim 8 (depends on 1) The testing circuit of claim 1 wherein the test controller is located at a high volume manufacturing tester. ### Claim 9 A method, comprising: coupling a digital to analog converter (DAC) an analog to digital converter (ADC) via at least one analog line; applying a code pattern having a plurality of sequential values to the digital to analog converter; switching a plurality of built-in test switches to couple at least one tap voltage from the DAC to a test bus and to couple a variable reference input voltage to the ADC; receiving at a test controller an output signal from the ADC and DAC resulting from application of the code pattern to the DAC and control of the plurality of built-in test switches; wherein the test controller is capable of configuring the plurality of built-in test switches between a test-mode operation and a normal-mode operation. ### Claim 10 (depends on 9) The method of claim 9, wherein the digital to analog converter comprises a plurality of resistors configured in a resistor string, a plurality of switches connected to the plurality of resistors, and decoder logic adapted to control the plurality of switches based on the code pattern to generate the at least one tap voltage. ### Claim 11 (depends on 10) The method of claim 10, wherein the analog to digital converter comprises a plurality of comparators to receive at least one tap voltage from the DAC and the variable reference input voltage. ### Claim 12 (depends on 11) The method of claim 11, wherein the test bus comprises an analog test bus and a digital test bus. ### Claim 13 (depends on 11) The method of claim 11, wherein the test controller in the test-mode operation is capable of determining whether the digital to analog converter (DAC) or the analog to digital converter (ADC) is faulty. ### Claim 14 (depends on 12) The method of claim 12, wherein the plurality of comparators can be tested by setting a set of the at least one tap voltage to mid code using the generated code pattern and sweeping one of the at least one tap voltage through a series of values. ### Claim 15 (depends on 12) The method of claim 12, wherein the plurality of switches, decode logic, plurality of resistors can be tested sweeping the code pattern through a series of values and measuring the response of the ADC and the DAC at the analog test bus and the digital test bus. ### Claim 16 A semiconductor die comprising: a digital to analog converter (DAC) comprising a plurality of resistors configured in a resistor string, a plurality of switches connected to the plurality of resistors, and decoder logic adapted to control the plurality of switches based on a code pattern to generate at least one tap voltage; an analog to digital converter (ADC) comprising a plurality of comparators to receive at least one tap voltage from the digital to analog converter and a variable reference input voltage; on-die circuitry capable of enabling the use of one tap voltage as an input to the plurality of comparators and to disconnect the plurality of comparators from an input voltage to be digitized; wherein the digital to analog converter and the analog to digital converter are coupled to a test controller via a test bus; and wherein the test controller is capable of configuring the on-die circuitry between a test-mode operation and a normal-mode operation. ### Claim 17 (depends on 16) The semiconductor die of claim 16, where the on-die circuitry is capable of coupling at least one tap voltage from the DAC to the test bus. ### Claim 18 (depends on 17) The semiconductor die of claim 17, wherein the test controller in the test-mode operation is capable of determining whether the digital to analog converter (DAC) or the analog to digital converter (ADC) is faulty. ### Claim 19 (depends on 18) The semiconductor die of claim 18, wherein the test bus comprises an analog test bus and a digital test bus. ### Claim 20 (depends on 19) The semiconductor die of claim 19, wherein the plurality of comparators can be tested by setting one of the at least one tap voltage to mid code using the generated code pattern and sweeping one of the at least one tap voltage through a series of values; and wherein the plurality of switches, decode logic, plurality of resistors can be tested sweeping the code pattern through a series of values and measuring the response of the ADC and the DAC at an analog test bus and at a digital test bus.