# US 2014/0191887 A1 · Mtr and rll code design and encoder and decoder

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- Number: US 2014/0191887 A1
- Document ID: US20140191887A1
- Status: Published application
- Kind: A1
- Application number: 14/151,656
- Filed: 2014-01-09
- Published: 2014-07-10
- Earliest claimed: 2011-04-21
- Assignees: SK hynix memory solutions inc.
- Applicants: SK Hynix Memory Solutions Inc.
- Inventors: Zheng Wu; Jason Bellorado; Marcus Marrow
- Web page: https://patentgrep.com/patent/US20140191887A1

## CPC

- H03M 5/145: {Conversion to or from block codes or representations thereof}
- H03M 7/20: Conversion to or from n-out-of-m codes
- H03M 7/46: Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

## Claims

### Claim 1

A system, comprising:
an interface configured to:
receive, for n=1, . . . , N where N is a length of a codeword, an array f(n); and
receive, for n=1, . . . , N where N is a length of a codeword, an array g(n); and
a processor configured to encode input data to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

### Claim 2 (depends on 1)

The system of claim 1, wherein f(n) is associated with a number of paths through a z1 state, in a trellis, which is associated with a run of zeros of run length 1 and g(n) is associated with a number of paths through a t1 state, in the trellis, which is associated with a run of ones of run length 1.

### Claim 3

A system, comprising:
an interface configured to:
receive, for n=1, . . . , N where N is a length of a codeword, an array f(n); and
receive, for n=1, . . . , N where N is a length of a codeword, an array g(n); and
a processor configured to decode a codeword using the array f(n) and the array g(n) to obtain user data.

### Claim 4 (depends on 3)

The system of claim 3, wherein f(n) is associated with a number of paths through a z1 state, in a trellis, which is associated with a run of zeros of run length 1 and g(n) is associated with a number of paths through a t1 state, in the trellis, which is associated with a run of ones of run length 1.

### Claim 5

A system, comprising:
a processor; and
a memory coupled with the processor, wherein the memory is configured to provide the processor with instructions which when executed cause the processor to:
determine, for a number N, a number of codewords of length N which satisfy a RLL constraint and a MTR constraint;
determine, based on the number of codewords, a number M for which a plurality of input data of length M can be uniquely mapped to a codeword; and
create a plurality of associations between the plurality of input data and the codewords.

### Claim 6 (depends on 5)

The system of claim 5, wherein the processor is configured to determine the number M, including by: using M=└log2 (the number of codewords)┘.

### Claim 7 (depends on 5)

The system of claim 5, wherein the processor is configured to determine the number of codewords, including by using non-return-to-zero, inverted (NRZI) format.