# US 2014/0191802 A1 · Narrow voltage range multi-level output pulse modulated amplifier with one-bit hysteresis quantizer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191802 A1 - Document ID: US20140191802A1 - Status: Published application - Kind: A1 - Application number: 13/738,450 - Filed: 2013-01-10 - Published: 2014-07-10 - Earliest claimed: 2013-01-10 - Assignees: Analog Devices Technology - Inventors: Dan Li; Jinhua Ni - Web page: https://patentgrep.com/patent/US20140191802A1 ## CPC - H03F 3/2171: {with field-effect devices (H03F3/2173 - H03F3/2178 take precedence)} - H03F 3/217: Class D power amplifiers; Switching amplifiers - H03F: AMPLIFIERS ## Abstract An amplifier system may include a power stage having inputs for three different supply voltages and an output for coupling to a load, a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels, a monitor to provide a first control signal to the controller based on an input voltage signal, and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal. ## Claims ### Claim 1 An amplifier system, comprising: a power stage having inputs for three different supply voltages and an output for coupling to a load; a controller to generate control signals to the power stage that cause the power stage to vary an output voltage applied to the load among more than three distinct voltage levels; a monitor to provide a first control signal to the controller based on an input voltage signal; and a feedback system to provide a second control signal to the controller based on comparison of the output voltage and the input signal. ### Claim 2 (depends on 1) The amplifier system of claim 1, wherein the feedback system comprises an one-bit quantizer. ### Claim 3 (depends on 2) The amplifier system of claim 2, wherein the one-bit quantizer comprises a plurality of comparators. ### Claim 4 (depends on 1) The amplifier system of claim 1, wherein the second control signal represents two quantization states. ### Claim 5 (depends on 1) The amplifier system of claim 1, wherein the controller generates the control signals by integrating the second control signal with a delayed code of the second control signal, to generate a hysteresis code, and integrating the hysteresis code with the first control signal. ### Claim 6 (depends on 1) The amplifier system of claim 1, wherein the power stage comprises a plurality of pairs of switches that switches the output between a plurality of maximum voltages and a plurality of minimum voltages. ### Claim 7 (depends on 1) The amplifier system of claim 1, further comprising a voltage booster powered by VDD to generate VPP. ### Claim 8 (depends on 1) The amplifier system of claim 1, wherein the first control signal represents more than two voltage range states. ### Claim 9 (depends on 1) The amplifier system of claim 1, wherein the feedback system comprises a summer having inputs for the input signal and inputs coupled to the output; and a tuner receiving an output from the summer. ### Claim 10 (depends on 1) The amplifier system of claim 1, wherein the controller generates the control signals according to pulse-density modulation, and the output voltage comprising a plurality of pulses, wherein a maximum voltage and a minimum voltage of each of the plurality of the pulses are two adjacent voltage levels of more than three distinct voltage levels, and the plurality of the pulses has more than two distinct combination of the maximum voltage and the minimum voltage as two adjacent voltage levels of more than three distinct voltage levels. ### Claim 11 A method, comprising: generating an output voltage to a load, by a power stage having inputs for three different supply voltages; generating control signals to the power stage, by a controller, to cause the power stage to vary the output voltage applied to the load among more than three distinct voltage levels; providing a first control signal to the controller, by a monitor, based on an input voltage signal; and providing a second control signal to the controller, by a feedback system, based on comparison of the output voltage and the input signal. ### Claim 12 (depends on 11) The method of claim 11, wherein the feedback system comprises an one-bit quantizer. ### Claim 13 (depends on 12) The method of claim 12, wherein the one-bit quantizer comprises a plurality of comparators. ### Claim 14 (depends on 11) The method of claim 11, wherein the second control signal represents two quantization states. ### Claim 15 (depends on 11) The method of claim 11, wherein the controller generates the control signals by integrating the second control signal with a delayed code of the second control signal, to generate a hysteresis code, and integrating the hysteresis code with the first control signal. ### Claim 16 (depends on 11) The method of claim 11, wherein the power stage comprises a plurality of pairs of switches that switches the output between a plurality of maximum voltages and a plurality of minimum voltages. ### Claim 17 (depends on 11) The method of claim 11, further comprising a voltage booster powered by VDD to generate VPP. ### Claim 18 (depends on 11) The method of claim 11, wherein the first control signal represents more than two voltage range states. ### Claim 19 (depends on 11) The method of claim 11, wherein the feedback system comprises a summer having inputs for the input signal and inputs coupled to the output; and a tuner receiving an output from the summer. ### Claim 20 (depends on 11) The method of claim 11, wherein the controller generates the control signals according to pulse-density modulation, and the output voltage comprising a plurality of pulses, wherein a maximum voltage and a minimum voltage of each of the plurality of the pulses are two adjacent voltage levels of more than three distinct voltage levels, and the plurality of the pulses has more than two distinct combination of the maximum voltage and the minimum voltage as two adjacent voltage levels of more than three distinct voltage levels. ### Claim 21 A non-transitory computer-readable medium storing instructions executable by a processor, the processor execute the instructions to: generating an output voltage to a load, by a power stage having inputs for three different supply voltages; generating control signals to the power stage, by a controller, to cause the power stage to vary the output voltage applied to the load among more than three distinct voltage levels; providing a first control signal to the controller, by a monitor, based on an input voltage signal; and providing a second control signal to the controller, by a feedback system, based on comparison of the output voltage and the input signal. ### Claim 22 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the feedback system comprises an one-bit quantizer. ### Claim 23 (depends on 22) The non-transitory computer-readable medium of claim 22, wherein the one-bit quantizer comprises a plurality of comparators. ### Claim 24 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the second control signal represents two quantization states. ### Claim 25 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the controller generates the control signals by integrating the second control signal with a delayed code of the second control signal, to generate a hysteresis code, and integrating the hysteresis code with the first control signal. ### Claim 26 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the power stage comprises a plurality of pairs of switches that switches the output between a plurality of maximum voltages and a plurality of minimum voltages. ### Claim 27 (depends on 21) The non-transitory computer-readable medium of claim 21, further comprising a voltage booster powered by VDD to generate VPP. ### Claim 28 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the first control signal represents more than two voltage range states. ### Claim 29 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the feedback system comprises a summer having inputs for the input signal and inputs coupled to the output; and a tuner receiving an output from the summer. ### Claim 30 (depends on 21) The non-transitory computer-readable medium of claim 21, wherein the controller generates the control signals according to pulse-density modulation, and the output voltage comprising a plurality of pulses, wherein a maximum voltage and a minimum voltage of each of the plurality of the pulses are two adjacent voltage levels of more than three distinct voltage levels, and the plurality of the pulses has more than two distinct combination of the maximum voltage and the minimum voltage as two adjacent voltage levels of more than three distinct voltage levels.