# US 2014/0191792 A1 · Semiconductor device and manufacturing method and operating method for the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191792 A1 - Document ID: US20140191792A1 - Status: Published application - Kind: A1 - Application number: 13/736,981 - Filed: 2013-01-09 - Published: 2014-07-10 - Earliest claimed: 2013-01-09 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Ching-Lin Chan; Chen-Yuan Lin; Cheng-Chi Lin; Shih-Chin Lien - Web page: https://patentgrep.com/patent/US20140191792A1 ## CPC - H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)} - H10D 30/0285: {using formation of insulating sidewall spacers} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 62/051: {Forming charge compensation regions, e.g. superjunctions} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/154: {Dispositions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 30/655: {having edge termination structures} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having a first type conductivity; a deep well formed in the substrate and having a second type conductivity opposite to the first type conductivity; a first well formed in the deep well, wherein the first well has at least one of the first type conductivity and the second type conductivity; a first doped electrode region formed in the first well and having the first type conductivity; a second doped electrode region having the second type conductivity, wherein the second doped electrode is formed in the first well and adjacent to the first doped electrode region; a high threshold voltage channel region formed in the first well and having the second type conductivity, wherein the high threshold voltage channel extends down from a surface of the substrate and covers parts of a surface of the second doped electrode, wherein a surface of the high threshold voltage channel having a first side, a second side opposite to the first side, a third side and the fourth side opposite to the third side, the first side and the second side are adjoined to the third side and the fourth side. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising at least two the high threshold voltage channel region. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising: a field layer formed in the first well and having the first type conductivity, wherein the field layer extends down from the surface of the substrate and covers a surface of the first doped electrode. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising: a third doped electrode region within the deep well and having the second conductive type, wherein the third doped electrode region extends down from the surface of the substrate and being spaced apart from the second doped electrode region with a distance. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, further comprising: a dielectric formed on the substrate and positioned between the second doped electrode region and the third doped electrode region. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, further comprising: a gate structure on the high threshold voltage channel region and the dielectric. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the gate structure is electrically connected to a voltage source, when the voltage source applies zero voltage to the gate structure, the semiconductor device provides an output current, wherein the higher area of the second doped electrode region covered by the high threshold voltage channel region, the higher output current the semiconductor device provides. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, further comprising: a top doped region having the first type conductivity, wherein the top doped region is formed in the deep well and positioned beneath the dielectric. ### Claim 9 A method for manufacturing semiconductor device, comprising: providing a substrate having a first type conductivity; forming a deep well having a second type conductivity opposite to the first type conductivity in the substrate, wherein the deep well extends down from a surface of the substrate; forming a first well having at least one of the first type conductivity and the second type conductivity in the deep well, wherein the first well extends down from the surface of the substrate; forming a high threshold voltage channel region having the second type conductivity, wherein the high threshold voltage channel region is formed in the first well and extends down from the surface of the substrate; forming a first doped electrode region having the first type conductivity in the deep well, wherein the first doped electrode region is in a region without the high threshold voltage channel region in the first well; forming a second doped electrode region having the second type conductivity in the deep well, wherein the second doped electrode region is adjacent to the first doped electrode region, and parts of the second doped electrode region are covered by the high threshold voltage channel region; wherein an output current provided by the semiconductor device is controlled by adjusting an area of the second doped electrode region covered by the high threshold voltage channel region. ### Claim 10 (depends on 9) The method for manufacturing semiconductor device according to claim 9, wherein a surface of the high threshold voltage channel having a first side, a second side opposite to the first side, a third side and a fourth side opposite to the third side, the first side and the second side are adjoined to the third side and the fourth side. ### Claim 11 (depends on 9) The method for manufacturing semiconductor device according to claim 9, wherein the step of forming the high threshold voltage channel region is performed before the step of forming the first doped electrode region and the second doped electrode region. ### Claim 12 (depends on 9) The method for manufacturing semiconductor device according to claim 9, further comprising: forming a field layer having the first type conductivity in the first well, wherein the first well extends down from the surface of the substrate and covers a surface of the first doped electrode. ### Claim 13 (depends on 12) The method for manufacturing semiconductor device according to claim 12, wherein the step of forming the field layer is performed before the step of forming the first doped electrode region and the second doped electrode region. ### Claim 14 (depends on 12) The method for manufacturing semiconductor device according to claim 12, further comprising: forming a third doped electrode region within the deep well and having the second conductive type, wherein the third doped electrode region extends down from the surface of the substrate and being spaced apart from the second doped electrode region with a distance. ### Claim 15 (depends on 14) The method for manufacturing semiconductor device according to claim 14, further comprising: forming a dielectric on the substrate, wherein the dielectric is positioned between the second doped electrode region and the third doped electrode region. ### Claim 16 (depends on 15) The method for manufacturing semiconductor device according to claim 15, further comprising: forming a gate structure on the high threshold voltage channel region and the dielectric. ### Claim 17 (depends on 16) The method for manufacturing semiconductor device according to claim 16, wherein the gate structure is electrically connected to a voltage source, when the voltage source applies zero voltage to the gate structure, the semiconductor provides an output current. ### Claim 18 (depends on 16) The method for manufacturing semiconductor device according to claim 16, further comprising: forming a top doped region having the first type conductivity, wherein the top doped region is formed in the deep well and positioned beneath the dielectric. ### Claim 19 An operating method for a semiconductor device, wherein the semiconductor device comprises: a substrate having a first type conductivity; a deep well formed in the substrate and having a second type conductivity opposite to the first type conductivity; a first well formed in the deep well and having at least one of the first type conductivity and the second type conductivity; a first doped electrode region formed in the first well and having the first type conductivity; a second doped electrode region having the second type conductivity, wherein the second dope electrode region is formed in the first well and adjacent to the first doped electrode region; a third doped electrode region formed within the deep well, wherein the third doped electrode region extends down from the surface of the substrate, being spaced apart from the second doped electrode region with a distance and having the second conductive type; a high threshold voltage channel region having the second type conductivity, extending down from the surface of the substrate and formed in the first well, the high threshold voltage channel covers parts of the surface of the second doped electrode, wherein a surface of the high threshold voltage channel having a first side, a second side opposite to the first side, a third side and a fourth side opposite to the third side, the first side and the second side are adjoined to the third side and the fourth side; the operating method for the semiconductor device comprises: applying a voltage to the gate structure; coupling the first doped electrode region to a first electrode, wherein the first electrode is one of an anode and a cathode; and coupling the third doped electrode region to a second electrode, wherein the second electrode is another of the anode and the cathode. ### Claim 20 (depends on 19) The operating method for a semiconductor device according to claim 19, wherein the semiconductor device provides an output current when the voltage is zero.