# US 2014/0191791 A1 · Adder > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191791 A1 - Document ID: US20140191791A1 - Status: Published application - Kind: A1 - Application number: 14/162,812 - Filed: 2014-01-24 - Published: 2014-07-10 - Earliest claimed: 2011-05-20 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Tatsuya Ohnuki - Web page: https://patentgrep.com/patent/US20140191791A1 ## CPC - G06G 7/14: for addition or subtraction (of vector quantities G06G7/22 {; computing the average by addition; differential amplifiers H03F3/45}) - G06F 1/32: Means for saving power - G06F 7/485: Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} - G06F 7/501: Half or full adders, i.e. basic adder cells for one denomination - H03K 21/10: comprising logic circuits - H10D 84/01: Manufacture or treatment - H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies - H10D 86/01: Manufacture or treatment - H10D 86/021: {of multiple TFTs} - H10D 86/0212: {comprising manufacture, treatment or coating of substrates} - H10D 86/0214: {using temporary substrates} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials} - H10D 86/0229: {characterised by control of the annealing or irradiation parameters} - G06F 2207/4802: Special implementations - H03K 3/356008: {ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed. ## Claims ### Claim 1 A central processing unit comprising: a register; and an arithmetic logic unit comprising an adder, wherein the adder comprises: a sum circuit electrically connected to a first power supply line and a second power supply line; a first input terminal electrically connected to the sum circuit; a second input terminal electrically connected to the sum circuit; a third input terminal electrically connected to the sum circuit; and a first output terminal electrically connected to the sum circuit; wherein the sum circuit comprises: a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; and a second transistor comprising a channel formation region comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and wherein the sum circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of a high-potential signal to any one of the first input terminal, the second input terminal, and the third input terminal or high-potential signals to the first input terminal, the second input terminal, and the third input terminal. ### Claim 2 (depends on 1) The central processing unit according to claim 1, further comprising: a first potential supply controller, wherein the sum circuit is electrically connected to the first power supply line through the first potential supply controller, and a second potential supply controller, wherein the sum circuit is electrically connected to the second power supply line through the second potential supply controller. ### Claim 3 (depends on 2) The central processing unit according to claim 2, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with the clock signal. ### Claim 4 (depends on 2) The central processing unit according to claim 2, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal. ### Claim 5 (depends on 1) The central processing unit according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc. ### Claim 6 A central processing unit comprising: a register; and an arithmetic logic unit comprising an adder, wherein the adder comprises: a sum circuit electrically connected to a first power supply line and a second power supply line; a carry circuit electrically connected to the first power supply line and the second power supply line; a first input terminal electrically connected to the sum circuit and the carry circuit; a second input terminal electrically connected to the sum circuit and the carry circuit; a third input terminal electrically connected to the sum circuit and the carry circuit; a first output terminal electrically connected to the sum circuit; and a second output terminal electrically connected to the carry circuit, wherein each of the sum circuit and the carry circuit comprises: a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; and a second transistor comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, wherein the sum circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of a high-potential signal to any one of the first input terminal, the second input terminal, and the third input terminal or high-potential signals to the first input terminal, the second input terminal, and the third input terminal, and wherein the carry circuit is configured to output a high-potential signal from the second output terminal in accordance with an input of high-potentials to any two or three of the first input terminal, the second input terminal, and the third input terminal. ### Claim 7 (depends on 6) The central processing unit according to claim 6, wherein the second output terminal is electrically connected to the third input terminal. ### Claim 8 (depends on 6) The central processing unit according to claim 6, further comprising: a first potential supply controller, wherein the sum circuit is electrically connected to the first power supply line through the first potential supply controller, and a second potential supply controller, wherein the sum circuit is electrically connected to the second power supply line through the second potential supply controller. ### Claim 9 (depends on 8) The central processing unit according to claim 8, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with the clock signal. ### Claim 10 (depends on 8) The central processing unit according to claim 8, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the sum circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the sum circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal. ### Claim 11 (depends on 6) The central processing unit according to claim 6, further comprising: a first potential supply controller, wherein the carry circuit is electrically connected to the first power supply line through the first potential supply controller, and a second potential supply controller, wherein the carry circuit is electrically connected to the second power supply line through the second potential supply controller. ### Claim 12 (depends on 11) The central processing unit according to claim 11, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with the clock signal. ### Claim 13 (depends on 11) The central processing unit according to claim 11, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal. ### Claim 14 (depends on 6) The central processing unit according to claim 6, wherein the oxide semiconductor layer comprises indium, gallium, and zinc. ### Claim 15 A central processing unit comprising: a register; and an arithmetic logic unit comprising an adder, wherein the adder comprises: a carry circuit electrically connected to a first power supply line and a second power supply line; a first input terminal electrically connected to the carry circuit; a second input terminal electrically connected to the carry circuit; a third input terminal electrically connected to the carry circuit; and a first output terminal electrically connected to the carry circuit, wherein the carry circuit comprises: a first transistor, one of a source and a drain of the first transistor is electrically connected to the first power supply line and the other of the source and the drain of the first transistor is electrically connected to the second power supply line; a second transistor comprising a channel formation region comprising an oxide semiconductor layer, one of a source and a drain of the second transistor is electrically connected to the third input terminal and the other of the source and the drain of the second transistor is electrically connected to a gate of the first transistor, and wherein the carry circuit is configured to output a high-potential signal from the first output terminal in accordance with an input of high-potential signals to any two or three of the first input terminal, the second input terminal, and the third input terminal. ### Claim 16 (depends on 15) The central processing unit according to claim 15, wherein the first output terminal is electrically connected to the third input terminal. ### Claim 17 (depends on 15) The central processing unit according to claim 15, further comprising: a first potential supply controller, wherein the carry circuit is electrically connected to the first power supply line through the first potential supply controller, and a second potential supply controller, wherein the carry circuit is electrically connected to the second power supply line through the second potential supply controller. ### Claim 18 (depends on 17) The central processing unit according to claim 17, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with the clock signal. ### Claim 19 (depends on 17) The central processing unit according to claim 17, wherein the first potential supply controller comprises a third transistor, wherein one of a source and a drain of the third transistor is electrically connected to the carry circuit and the other of the source and the drain of the third transistor is electrically connected to the first power supply line, wherein a gate of the third transistor is configured to be supplied with a clock signal, wherein the second potential supply controller comprises a fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the carry circuit and the other of the source and the drain of the fourth transistor is electrically connected to the second power supply line, and wherein a gate of the fourth transistor is configured to be supplied with an inverted clock signal. ### Claim 20 (depends on 15) The central processing unit according to claim 15, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.