# US 2014/0191786 A1 · Phase frequency detector circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191786 A1 - Document ID: US20140191786A1 - Status: Published application - Kind: A1 - Application number: 14/142,552 - Filed: 2013-12-27 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: NXP B.V. - Applicants: NXP B.V. - Inventors: Louis Praamsma; Nikola Ivanisevic - Web page: https://patentgrep.com/patent/US20140191786A1 ## CPC - H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump} - H03D 13/004: {the logic means delivering pulses at more than one terminal, e.g. up and down pulses} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66) ## Abstract A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion. ## Claims ### Claim 1 A phase-frequency detector (PFD) circuit comprising: a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference; and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion. ### Claim 2 (depends on 1) The PFD circuit of claim 1, wherein the PFD portion comprises first and second D flip-flops adapted to generate first and second control signals, respectively, and wherein the delay and reset portion comprises: a first delay element adapted to delay the first control signal by a first predetermined delay time; a second delay element adapted to delay the second control signal by a second predetermined delay time; and a reset signal generator adapted to generate a first reset signal for the first D flip-flop based on the first control signal and the delayed second control signal, and to generate a second reset signal for the second D flip-flop based on the second control signal and the delayed first control signal. ### Claim 3 (depends on 2) The PFD circuit of claim 2, wherein the reset signal generator comprises first and second AND logic gates adapted to generate the first and second reset signals respectively, wherein the first control signal and the delayed second control signal are provided to the inputs of first AND logic gate, and wherein the second control signal and the delayed first control signal are provided to the inputs of second AND logic gate. ### Claim 4 (depends on 2) The PFD circuit of claim 2, wherein the first and second predetermined delay times are substantially equal to each other. ### Claim 5 (depends on 2) The PFD circuit of claim 2, wherein at least one of the first and second delay elements comprises one or more inverters. ### Claim 6 (depends on 1) The PDF circuit according to claim 1, further comprising a charge pump adapted to supply current at an output of the PFD circuit according to the generated control signals. ### Claim 7 (depends on 1) The PDF circuit according to claim 1, wherein the PFD portion comprises a tri-state PFD. ### Claim 8 (depends on 1) A Phase Locked Loop, PLL, circuit comprising a PFD circuit according to claim 1. ### Claim 9 (depends on 1) An optical communications receiver device comprising a PFD circuit according to claim 1. ### Claim 10 A method of phase-frequency detection for a phase locked loop, PLL, the method comprising: operating a PFD circuit portion to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference; delaying the generated control signals; generating reset signals for resetting the PFD circuit portion based on a combination of the control signals and the delayed control signals; and providing the generated reset signals to the PFD circuit portion. ### Claim 11 (depends on 10) A computer program product for phase-frequency detection, wherein the computer program product comprises a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to perform all of the steps of claim 10. ### Claim 12 (depends on 11) A computer system for phase-frequency detection, the system comprising: a computer program product according to claim 11; and one or more processors adapted to perform an operation, the operation comprising: operating a PFD circuit portion to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference; delaying the generated control signals; generating reset signals for resetting the PFD circuit portion based on a combination of the control signals and the delayed control signals; and providing the generated reset signals to the PFD circuit portion.