# US 2014/0191781 A1 · Active shield with electrically configurable interconnections

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- Number: US 2014/0191781 A1
- Document ID: US20140191781A1
- Status: Published application
- Kind: A1
- Application number: 14/238,736
- Filed: 2012-11-16
- Published: 2014-07-10
- Earliest claimed: 2011-11-18
- Assignees: Tubitak
- Applicants: Tubitak
- Inventors: Umut Guvenc
- Web page: https://patentgrep.com/patent/US20140191781A1

## CPC

- G06F 21/60: Protecting data
- H10W 42/405: {using active circuits}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Introduced is an active shield method providing security to a security critical integrated circuit against some physical attacks like probing, manipulation and modification, while providing the ability to detect any physical modification made on the active shield itself. Electrically controllable switching circuits are used to construct the upper layer conductive bit lines with electrically selectable different interconnection configurations. These bit lines arranged in a shielding pattern are used to carry a test data between a transmitter circuitry and a number of receiver circuitries which verify the integrity of the shielding lines to provide the security for the integrated circuit. By changing the selected interconnection configuration of the bit lines with a select signal produced by the transmitter, the self detection ability of the proposed active shield is provided as a countermeasure against the vulnerability to physical modification made on the active shield itself.

## Claims

### Claim 1

An integrated circuit comprising an active shield said active shield comprising upper layer conductive lines (2) arranged in a shielding manner to cover at least a, part of a security critical circuit (3) arranged in lower layers of an integrated circuit (1); electrically controllable switching circuits arranged to select the connections of ones of said upper layer conductive lines (2) to other ones of said upper layer conductive lines (2) to form a multiplicity of data bit lines; internal data buses (12) arranged in lower lavers of the integrated circuit (1); at least one transmitter (7) and a multiplicity of receivers (8), wherein the transmitter (7) is arranged to transmit test data to the receivers (8) via both the said data bit lines and said internal data buses (12). the said at least one transmitter (7) comprises means for generating a. select signal (11) and means for transmitting the select signal (11) to the said receivers (8) and the said electrically controllable switching circuits (5) via a. data path arranged in lower lavers of the integrated circuit (1), and the said at least one transmitter (7) is arranged to change the value of the said select signal (11) in regular or random time intervals; the said electrically controllable switching circuits are arranged to select different ones of said upper layer conductive lines (2) for the different values of the said select signal (11) to change the interconnection configuration (9,10) of the said bit lines; the said receivers (8) comprises means for reordering the said bit lines according to the said interconnection configuration (9,10) selected by the said select signal (11) and, the said receivers (8) are configured to compare the test data received from the said bit lines with the actual test data received from the said internal data buses (12), in order to verify the integrity of the said upper layer conductive lines (2).

### Claim at position 2

2-7. (canceled)