# US 2014/0191778 A1 · On chip electrostatic discharge (esd) event monitoring > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191778 A1 - Document ID: US20140191778A1 - Status: Published application - Kind: A1 - Application number: 13/733,954 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: John B. DeForge; Junjun Li; Alain F. Loiseau; Kirk D. Peterson - Web page: https://patentgrep.com/patent/US20140191778A1 ## CPC - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01R 31/002: {where the device under test is an electronic circuit} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An approach for monitoring electrostatic discharge (ESD) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an ESD pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure. The approach further includes circuit source and logic gates of the canary device, connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure. The approach further includes a logic gate of the ESD transistor, connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure. In addition, the enable signal is also connected to the input terminal through a resistor of the circuit structure. ## Claims ### Claim 1 A circuit structure for monitoring an electrostatic discharge (ESD) event in a manufacturing environment of an integrated circuit package, the circuit structure comprising: a canary device for exhibiting an impedance shift when affected by an ESD pulse of the ESD event, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure; and wherein circuit source and logic gates of the canary device are connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure, wherein logic gate of the ESD transistor is connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure, and wherein the enable signal is also connected to the input terminal through a resistor of the circuit structure. ### Claim 2 (depends on 1) The circuit structure according to claim 1, wherein the circuit structure comprises multiple canary devices for monitoring the ESD event in the integrated circuit package. ### Claim 3 (depends on 2) The circuit structure according to claim 2, wherein the multiple canary devices are arranged to distinguish the ESD event of various magnitudes. ### Claim 4 (depends on 1) The circuit structure according to claim 1, wherein the canary device is connected in series with one or more diodes of the circuit structure. ### Claim 5 (depends on 1) The circuit structure according to claim 1, wherein the impendence shift exhibited by the canary device is exhibited during normal operation of the integrated circuit. ### Claim 6 (depends on 5) The circuit structure according to claim 5, wherein the large impedance shift does not impact the normal operation of the integrated circuit. ### Claim 7 (depends on 1) The circuit structure according to claim 1, wherein the integrated circuit includes any memory storage. ### Claim 8 (depends on 1) The circuit structure according to claim 1 further comprising a power clamp. ### Claim 9 (depends on 8) The circuit structure according to claim 8, wherein the power clamp is an ESD structure that is used to create current discharge path during an ESD event between input and output terminal of the circuit structure. ### Claim 10 (depends on 1) The circuit structure according to claim 1, wherein the circuit structure amplifies leakage of current to the canary device, and wherein the leaked current is amplified to ensure that an input terminal of the integrated circuit loses functionality when the leaked current flows through the canary device. ### Claim 11 A method for monitoring electrostatic discharge (ESD) event in a manufacturing environment of an integrated circuit package, the method comprising: a circuit structure; a canary device for exhibiting an impedance shift when affected by an ESD pulse of the ESD event, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure; and wherein circuit source and logic gates of the canary device are connected to a circuit drain of ESD transistor of the circuit structure, wherein circuit source of the ESD transistor is connected to an output terminal of the circuit structure, wherein logic gate of the ESD transistor is connected to an enable signal of the circuit structure, and wherein the enable signal is connected to the output terminal through a capacitor of the circuit structure, and wherein the enable signal is also connected to the input terminal through a resistor of the circuit structure. ### Claim 12 (depends on 11) The method according to claim 11, wherein the circuit structure comprises multiple canary devices for monitoring the ESD event in the integrated circuit package. ### Claim 13 (depends on 12) The method according to claim 12, wherein the multiple canary devices are arranged to distinguish the ESD event of various magnitudes of the circuit structure. ### Claim 14 (depends on 11) The method according to claim 11, wherein the canary device is connected in series with one or more diodes of the circuit structure. ### Claim 15 (depends on 11) The method according to claim 11, wherein the impendence shift exhibited by the canary device is exhibited during normal operation of the integrated circuit. ### Claim 16 (depends on 15) The method according to claim 15, wherein the large impedance shift does not Impact the normal operation of the integrated circuit. ### Claim 17 (depends on 1) The method according to claim 1, wherein the integrated circuit includes any memory storage. ### Claim 18 (depends on 11) The method according to claim 11, further comprising a power clamp. ### Claim 19 (depends on 8) The circuit structure according to claim 8, wherein the power clamp is an ESD structure that is used to create current discharge path during an ESD event between input and output terminal of the circuit structure. ### Claim 20 (depends on 11) The method according to claim 11, wherein the circuit structure amplifies leakage of current to the canary device, and wherein the leaked current is amplified to ensure that an input terminal of the integrated circuit loses functionality when the leaked current flows through the canary device.