# US 2014/0191419 A1 · 3d integrated circuit package with window interposer

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- Number: US 2014/0191419 A1
- Document ID: US20140191419A1
- Status: Published application
- Kind: A1
- Application number: 13/995,917
- Filed: 2011-12-22
- Published: 2014-07-10
- Earliest claimed: 2011-12-22
- Assignees: Intel Corporation
- Inventors: Debendra Mallik; Ram S. Viswanath; Sriram Srinivasan; Mark T. Bohr; Andrew W. Yeoh; Sairam Agraharam
- Web page: https://patentgrep.com/patent/US20140191419A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate;
a top semiconductor die disposed above the substrate;
an interposer having a window, the interposer disposed between and interconnected to the substrate and the top semiconductor die; and
a bottom semiconductor die disposed in the window of the interposer, and interconnected to the top semiconductor die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the bottom semiconductor die comprises no through silicon vias (TSVs) and is not interconnected directly to the substrate.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein an active side of the bottom semiconductor die faces an active side of the top semiconductor die, and away from the substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the bottom semiconductor die comprises through silicon vias (TSVs) and is interconnected directly to the substrate.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein an active side of the bottom semiconductor die faces away from an active side of the top semiconductor die, and toward the substrate.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the bottom semiconductor die is disposed in a closed window of the interposer.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein the top semiconductor die completely overlaps the bottom semiconductor die.

### Claim 8 (depends on 6)

The semiconductor package of claim 6, further comprising one or more additional bottom semiconductor die, the one or more additional bottom semiconductor die disposed in one or more additional closed windows of the interposer.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the top semiconductor die completely overlaps the bottom semiconductor die as well as the one or more additional bottom semiconductor die.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the bottom semiconductor die is disposed in an open window of the interposer.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the top semiconductor die only partially overlaps the bottom semiconductor die.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, further comprising one or more additional top semiconductor die, the one or more additional top semiconductor die disposed above the substrate in a same plane as the top semiconductor die and interconnected to the interposer.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the top semiconductor die completely overlaps the bottom semiconductor die.

### Claim 14 (depends on 1)

The semiconductor package of claim 1, wherein the interposer comprises two or more discrete units, and wherein the bottom semiconductor die is disposed in a closed window of the two or more discrete units of the interposer.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the top semiconductor die completely overlaps the bottom semiconductor die.

### Claim 16

A semiconductor package, comprising:
a substrate;
a top semiconductor die disposed above the substrate;
an interposer disposed between and interconnected to the substrate and the top semiconductor die; and
a bottom semiconductor die disposed in a same plane as the interposer, and interconnected to the top semiconductor die.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the bottom semiconductor die is disposed adjacent to, but not within, the interposer.

### Claim 18 (depends on 16)

The semiconductor package of claim 16, wherein the top semiconductor die only partially overlaps the bottom semiconductor die.

### Claim 19 (depends on 16)

The semiconductor package of claim 16, wherein the bottom semiconductor die comprises no through silicon vias (TSVs) and is not interconnected directly to the substrate.

### Claim 20 (depends on 16)

The semiconductor package of claim 16, wherein an active side of the bottom semiconductor die faces an active side of the top semiconductor die, and away from the substrate.

### Claim 21 (depends on 16)

The semiconductor package of claim 16, wherein the bottom semiconductor die comprises through silicon vias (TSVs) and is interconnected directly to the substrate.

### Claim 22 (depends on 16)

The semiconductor package of claim 16, wherein an active side of the bottom semiconductor die faces away from an active side of the top semiconductor die, and toward the substrate.

### Claim 23

A semiconductor die pairing, comprising:
a top semiconductor die;
an interposer disposed below and interconnected to the top semiconductor die; and
a bottom semiconductor die disposed in a same plane as the interposer, and interconnected to the top semiconductor die.

### Claim 24 (depends on 23)

The semiconductor die pairing of claim 23, wherein the bottom semiconductor die is disposed in a closed window of the interposer.

### Claim 25 (depends on 24)

The semiconductor die pairing of claim 24, further comprising one or more additional bottom semiconductor die, the one or more additional bottom semiconductor die disposed in one or more additional closed windows of the interposer.

### Claim 26 (depends on 23)

The semiconductor die pairing of claim 23, wherein the bottom semiconductor die is disposed in an open window of the interposer.

### Claim 27 (depends on 23)

The semiconductor die pairing of claim 23, further comprising one or more additional top semiconductor die, the one or more additional top semiconductor die disposed in a same plane as the top semiconductor die and interconnected to the interposer.

### Claim 28 (depends on 23)

The semiconductor die pairing of claim 23, wherein the interposer comprises two or more discrete units, and wherein the bottom semiconductor die is disposed in a closed window of the two or more discrete units of the interposer.

### Claim 29 (depends on 23)

The semiconductor die pairing of claim 23, wherein the bottom semiconductor die is disposed adjacent to, but not within, the interposer.

### Claim 30 (depends on 23)

The semiconductor die pairing of claim 23, wherein the bottom semiconductor die comprises no through silicon vias (TSVs), and wherein an active side of the bottom semiconductor die faces an active side of the top semiconductor die.