# US 2014/0191416 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191416 A1 - Document ID: US20140191416A1 - Status: Published application - Kind: A1 - Application number: 14/202,555 - Filed: 2014-03-10 - Published: 2014-07-10 - Earliest claimed: 2011-08-03 - Assignees: Elpida Memory, Inc. - Applicants: Elpida Memory, Inc. - Inventors: Tomohiro KITANO; Hisayuki NAGAMINE - Web page: https://patentgrep.com/patent/US20140191416A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10D 89/10: Integrated device layouts - H10W 20/423: {Shielding layers} - H10W 20/43: Layouts of interconnections - H10W 20/496: {Capacitor integral with wiring layers} - H10W 90/00: Package configurations - H10B 12/50: {Peripheral circuit region structures} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/635: {Through-vias} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate; a plurality of through silicon vias formed through the semiconductor substrate and spaced at first predetermined intervals in a first direction; a plurality of power supply connection pads each having a first size, and the power supply connection pads being connected to first selected ones of the through silicon vias; a plurality of input/output connection pads each having a second size, smaller than the first size, and the input/output connection pads being connected to second selected ones of the through silicon vias other than the first selected ones of the through silicon vias; a plurality of input/output circuits; and a plurality of wires connecting the input/output circuits to respective ones of the input/output connection pads, and wherein the wires include adjustment portions to provide distance compensation between the input/output circuits and respective input/output connection pads. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1 wherein the power supply connection pads comprise VDD and VSS power supply connection pads. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1 wherein the power supply connection pads comprise VDDQ and VSSQ power supply connection pads. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1 wherein the power supply connection pads comprise VDD, VSS, VDDQ and VSSQ power supply connection pads. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1 wherein the input/output connection pads comprise address/command connection pads. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1 wherein the input/output connection pads comprise DQ connection pads. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1 wherein the semiconductor device is a DRAM chip. ### Claim 8 (depends on 1) The semiconductor device as claimed in claim 1 wherein the semiconductor device is a controller chip. ### Claim 9 (depends on 1) The semiconductor device as claimed in claim 1 wherein the semiconductor device is a DRAM. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1 wherein the through silicon vias are spaced at second predetermined intervals in a second direction orthogonal to the first direction. ### Claim 11 (depends on 1) The semiconductor device as claimed in claim 1 wherein the second predetermined interval is greater than the first predetermined interval. ### Claim 12 (depends on 11) The semiconductor device as claimed in claim 11 wherein the wires are located within the space defined by the second predetermined interval. ### Claim 13 (depends on 1) The semiconductor device as claimed in claim 1 wherein the adjustment portions are each located in an area defined by the difference between the first size and the second size. ### Claim 14 (depends on 1) The semiconductor device as claimed in claim 1 wherein the wires each have equal length and width, and the adjustment portions each comprise surplus portions of wire not required to span the distance between each input/output circuit and respective input/output connection pad. ### Claim 15 (depends on 14) The semiconductor device as claimed in claim 14 wherein the surplus portion of wire is bent in a meandering manner. ### Claim 16 (depends on 14) The semiconductor device as claimed in claim 14 wherein the surplus portion of wire is formed into a swirl around a respective input/output connection pad. ### Claim 17 (depends on 1) The semiconductor device as claimed in claim 1 wherein the adjustment portions each comprise a capacitor. ### Claim 18 (depends on 17) The semiconductor device as claimed in claim 17 wherein the capacitor comprises a comb-shaped capacitor. ### Claim 19 (depends on 17) The semiconductor device as claimed in claim 17 wherein the adjustment portions each comprise a parallel plate structure. ### Claim 20 (depends on 1) The semiconductor device as claimed in claim 1 wherein the wires each have substantially the same resistance. ### Claim 21 (depends on 1) The semiconductor device as claimed in claim 1 wherein the wires each have substantially the same capacitance. ### Claim 22 (depends on 1) The semiconductor device as claimed in claim 1 wherein the wires each have substantially the same time constant.