# US 2014/0191413 A1 · Method for producing a semiconductor device comprising a conductor layer in the semiconductor body and semiconductor body

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- Number: US 2014/0191413 A1
- Document ID: US20140191413A1
- Status: Published application
- Kind: A1
- Application number: 14/124,666
- Filed: 2012-05-16
- Published: 2014-07-10
- Earliest claimed: 2011-06-16
- Assignees: Ams AG
- Inventors: Rainer Minixhofer; Ewald Stückler; Martin Schrems; Günther Koppitsch; Jochen Kraft; Jordi Teva
- Web page: https://patentgrep.com/patent/US20140191413A1

## CPC

- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2128: {Coaxial through-semiconductor vias}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A cutout (11), which penetrates the semiconductor body, is present in the semiconductor body (1). A conductor layer (6), which is electrically conductively connected to a metal plane (3) on or over the semiconductor body, screens the semiconductor body electrically from the cutout. The conductor layer can be metal, optionally with a barrier layer (6a), or a doped region of the semiconductor body.

## Claims

### Claim 1

A method for the production of a semiconductor component, wherein
a semiconductor body is provided on at least one upper side or underside with metal planes in a dielectric;
a cutout is produced in the dielectric and in the semiconductor body, so that the cutout penetrates the semiconductor body, and the semiconductor body has a surface in the cutout;
a conductor layer is produced at this surface in direct connection with the semiconductor body; and
the conductor layer is electrically conductively connected to one of the metal planes.

### Claim 2 (depends on 1)

The method according to claim 1, wherein
the conductor layer is produced by implanting a dopant in the semiconductor body.

### Claim 3 (depends on 1)

The method according to claim 1, wherein
the conductor layer is produced by applying a barrier layer on the surface of the semiconductor body and applying a metal on the barrier layer.

### Claim 4 (depends on 3)

The method according to claim 3, wherein
the semiconductor body is silicon and a silicide is formed with the conductor layer.

### Claim 5 (depends on 1, 2, 3, 4)

The method according to one of claims 1 to 4, wherein
the conductor layer in the cutout is covered with a spacer made of dielectric material, and a metal layer is applied and structured, so that the metal layer is present within the cutout and electrically insulated from the conductor layer by the spacer and is outside the cutout electrically conductively connected to at least one of the metal planes.

### Claim 6

A method for the production of a semiconductor component, wherein
a semiconductor body is provided with a dielectric at an upper side and at an underside opposite the upper side and with metal planes located at least on one side of the semiconductor body in the dielectric;
a cutout is formed in the dielectric present at the upper side and in the semiconductor body, so that the cutout penetrates the semiconductor body and is limited by the dielectric present at the underside;
a conductor layer is applied and structured in such a manner that it screens the semiconductor body toward the cutout and is electrically conductively connected to at least one of the metal planes;
the conductor layer in the cutout is covered with a spacer formed from dielectric material; and
a metal layer is applied and structured, so that the metal layer is present within the cutout and electrically insulated from the conductor layer by the spacer, and is outside the cutout electrically conductively connected to at least one of the metal planes.

### Claim 7 (depends on 6)

The method according to claim 6, wherein
at least one of the metal planes is provided in the dielectric arranged at the underside of the semiconductor body;
with the production of the spacer, a region of said metal plane is exposed; and
the metal layer is placed and structured in such a way that the metal layer forms a connection contact on the exposed region.

### Claim 8 (depends on 1, 2, 3, 4, 5, 6, 7)

The method according to one of claims 1 to 7, wherein
after the production of the cutout and before the production of the conductor layer, one of the metal planes is removed in the region of the cutout; and
the conductor layer is arranged in such a way that it forms a contact to said metal plane vertically with respect to said metal plane.

### Claim 9 (depends on 1, 2, 3, 4, 5, 6, 7, 8)

The method according to one of claims 1 to 8, wherein
the metal layer in the cutout is covered with a further spacer formed from dielectric material; and
a further metal layer is arranged and structured, so that the further metal layer is present within the cutout and electrically insulated from the metal layer by the further spacer and is outside the cutout electrically conductively connected to at least one of the metal planes.

### Claim 10 (depends on 9)

The method according to claim 9, wherein
the conductor layer, the metal layer and the further metal layer are contacted with different metal planes on both sides of the semiconductor body.

### Claim 11 (depends on 9)

The method according to claim 9, wherein
the conductor layer, the metal layer and the further metal layer are contacted with the same metal planes at least on one side of the semiconductor body.

### Claim 12

A semiconductor device, comprising
a semiconductor body;
at least one metal plane on or above the semiconductor body;
a cutout completely penetrating the semiconductor body between an upper side and an underside opposite the upper side, so that the semiconductor body has a surface formed by the cutout;
a conductor layer, which is electrically conductively connected to one of the metal planes, electrically screening the semiconductor body from the cutout; and
a metal layer arranged in the cutout);
characterized in that
the conductor layer is arranged directly on the surface of the semiconductor body formed by the cutout; and
the metal layer is electrically insulated from the conductor layer by a spacer formed from dielectric material.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein
the conductor layer is formed as a doped region of the semiconductor body.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12, wherein
the semiconductor body is silicon, and
the conductor layer comprises a barrier layer arranged on the semiconductor body and a metal.

### Claim 15 (depends on 12, 13, 14)

The semiconductor device according to one of claims 12 to 14, wherein
the conductor layer and the metal layer form a through-connection.

### Claim 16 (depends on 12, 13, 14, 15)

The semiconductor device according to one of claims 12 to 15, wherein
the conductor layer and the metal layer form a capacitor.

### Claim 17 (depends on 12, 13, 14, 15, 16)

The semiconductor device according to one of claims 12 to 16, wherein
the conductor layer is electrically conductively connected to one of the metal planes only on one side of the semiconductor body.