# US 2014/0191412 A1 · Interconnection structures and fabrication method thereof

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- Number: US 2014/0191412 A1
- Document ID: US20140191412A1
- Status: Published application
- Kind: A1
- Application number: 14/060,975
- Filed: 2013-10-23
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: MING ZHOU
- Web page: https://patentgrep.com/patent/US20140191412A1

## CPC

- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad.

## Claims

### Claim 1

A method for fabricating an interconnection structure, comprising:
providing a semiconductor substrate have certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices;
forming a first conductive layer on the semiconductor substrate forming a second conductive layer by doping the first conductive layer to have smaller grain sizes;
forming an interconnection pad by patterning the second conductive layer; and
forming certain structure on the interconnection pad.

### Claim 2 (depends on 1)

The method according to claim 1, wherein forming certain structure on the interconnection pad further includes:
bonding a connection wire on the interconnection pad to form a wire bonding structure.

### Claim 3 (depends on 1)

The method according to claim 1, wherein forming certain structure on the interconnection pad further includes:
forming a solder ball on the interconnection pad to form a solder ball/solder pad interconnection structure.

### Claim 4 (depends on 1)

The method according to claim 1, wherein:
the first conductive layer is formed by a physical vapor deposition process.

### Claim 5 (depends on 1)

The method according to claim 1, after forming the second conductive layer, further including:
annealing the second conductive layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
the first conductive layer and the second conductive layer are made of aluminum.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
doping ions of the first conductive layer is boron ions.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
process for doping the first conductive layer is an ion implantation process.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
the first conductive layer is made of copper.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
grain sizes of the second conductive layer is approximately 0.1-0.9 of grain sizes of the first conductive layer.

### Claim 11 (depends on 1)

The method according to claim 1, wherein forming the second conductive layer further includes:
doping the first connective layer in situ to form the second conductive layer.

### Claim 12 (depends on 4)

The method according to claim 4, wherein:
protection gas for annealing the second conductive layer is helium or nitrogen.

### Claim 13 (depends on 7)

The method according to claim 7, wherein:
an energy of the ion implantation process is in a range of approximately 5 KeV˜50 KeV, and dose is less than approximately 1E27 atoms/cm2.

### Claim 14 (depends on 12)

The method according to claim 12, wherein:
a gas flow of helium or nitrogen is in a range of approximately 100 sccm˜5000 sccm;
an annealing temperature is in a range of approximately 250° C.˜450° C.; and
an annealing time is in a range of approximately 15 s˜300 s.

### Claim 15

An interconnection structure, comprising:
a semiconductor substrate have certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices;
a doped interconnection pad with smaller grain sizes, and
a connection wire bonded on the interconnection pad,
wherein:
the interconnection pad is formed by: forming a first conductive layer on the semiconductor substrate, doping the first conductive layer with certain types of ions to form a second conductive layer, and patterning the second conductive layer.

### Claim 16 (depends on 15)

The semiconductor structure according to claim 15, wherein:
the interconnection pad is made of aluminum.

### Claim 17 (depends on 15)

The semiconductor structure according to claim 15, wherein:
doping process for doping the first conductive layer is an ion implantation process.

### Claim 18 (depends on 15)

The semiconductor structure according to claim 15, wherein:
doping ions of the first conductive layer are boron ions.

### Claim 19 (depends on 15)

The semiconductor structure according to claim 15, wherein:
grain sizes of the interconnection pad are smaller than grain sizes of the first conductive layer.

### Claim 20 (depends on 15)

The semiconductor structure according to claim 15, wherein:
the first conductive layer is in situ doped to form the conductive layer.