# US 2014/0191410 A1 · Damage monitor structure for through-silicon via (tsv) arrays

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- Number: US 2014/0191410 A1
- Document ID: US20140191410A1
- Status: Published application
- Kind: A1
- Application number: 13/977,595
- Filed: 2011-12-27
- Published: 2014-07-10
- Earliest claimed: 2011-12-27
- Inventors: Gerald S. Leatherman; Christopher C. Pelto
- Web page: https://patentgrep.com/patent/US20140191410A1

## CPC

- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Described herein are techniques related to techniques for monitoring damage to circuitry or structure neighboring one or more through-silicon vias (TSVs) caused by TSV-related processing. Additionally, techniques for confining diffusion of moisture or chemical from one or more TSVs during TSV-related processing are also described. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

## Claims

### Claim at position 1

1-38. (canceled)

### Claim 39

A device comprising:
a multi-layer semiconductor structure;
one or more through-silicon vias (TSVs) traversing through the multi-layer semiconductor structure; and
an electrically conductive chain embedded in the multi-layer semiconductor structure and around the one or more TSVs.

### Claim 40 (depends on 39)

A device as recited in claim 39, wherein the electrically conductive chain comprises:
a plurality of metal lines; and
a plurality of vias each of which coupling respective two of the plurality of metal lines such that the plurality of metal lines are electrically coupled in series forming a series resistor.

### Claim 41 (depends on 39)

A device as recited in claim 39, wherein the electrically conductive chain comprises: a plurality of metal lines, wherein the plurality of metal lines are coupled in a staircase-like matter such that the plurality of metal lines are embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 42 (depends on 39)

A device as recited in claim 39 further comprising:
a guard ring embedded in the multi-layer semiconductor structure, between the one or more TSVs and the electrically conductive chain, and encompassing the one or more TSVs.

### Claim 43 (depends on 39)

A device as recited in claim 39, further comprising a guard ring, wherein the guard ring comprises:
a continuous line of metal embedded in a first layer of the multi-layer semiconductor structure; and
a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 44 (depends on 39)

A device as recited in claim 39, further comprising a guard ring, wherein the guard ring comprises:
a continuous line of dielectric embedded in a first layer of the multi-layer semiconductor structure; and
a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 45 (depends on 39)

A device as recited in claim 39, further comprising a guard ring, wherein the guard ring is embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 46 (depends on 39)

A device as recited in claim 39, further comprising a guard ring, wherein the guard ring hermetically seals the one or more TSVs such that moisture and contaminants related to fabrication of the TSVs are prevented from diffusing outside of the guard ring.

### Claim 47

A device comprising:
a multi-layer semiconductor structure;
one or more through-silicon vias (TSVs) traversing through the multi-layer semiconductor structure; and
a guard ring embedded in the multi-layer semiconductor structure and encompassing the one or more TSVs.

### Claim 48 (depends on 47)

A device as recited in claim 47, wherein the guard ring comprises:
a continuous line of metal embedded in a first layer of the multi-layer semiconductor structure; and
a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 49 (depends on 47)

A device as recited in claim 47, wherein the guard ring comprises:
a continuous line of dielectric embedded in a first layer of the multi-layer semiconductor structure; and
a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 50 (depends on 47)

A device as recited in claim 47, wherein the guard ring is embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 51 (depends on 47)

A device as recited in claim 47, wherein the guard ring hermetically seals the one or more TSVs such that moisture and contaminants related to fabrication of the TSVs are prevented from diffusing outside of the guard ring.

### Claim 52 (depends on 47)

A device as recited in claim 47 further comprising:
an electrically conductive chain embedded in the multi-layer semiconductor structure and around the one or more TSVs and the guard ring.

### Claim 53 (depends on 47)

A device as recited in claim 47, further comprising an electrically conductive chain, wherein the electrically conductive chain comprises:
a plurality of metal lines; and
a plurality of vias each of which coupling respective two of the plurality of metal lines such that the plurality of metal lines are electrically coupled in series forming a series resistor.

### Claim 54 (depends on 47)

A device as recited in claim 47, further comprising an electrically conductive chain that includes a plurality of metal lines, wherein the plurality of metal lines are coupled in a staircase-like matter such that the plurality of metal lines are embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 55

A method comprising:
providing a multi-layer semiconductor structure;
forming an electrically conductive chain that is embedded in the multi-layer semiconductor structure and around a through-silicon via region of the multi-layer semiconductor structure; and
forming one or more through-silicon vias (TSVs) that traverse through the through-silicon via region of the multi-layer semiconductor structure.

### Claim 56 (depends on 55)

A method as recited in claim 55 further comprising:
determining, based on an electrical property related to the electrically conductive chain, whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs.

### Claim 57 (depends on 55)

A method as recited in claim 55, further comprising determining whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs, wherein the determining comprises:
measuring a first resistive value of the electrically conductive chain before forming the one or more TSVs;
measuring a second resistive value of the electrically conductive chain after forming the one or more TSVs; and
detecting existence of the damage when the second resistive value is different than the first resistive value.

### Claim 58 (depends on 55)

A method as recited in claim 55, further comprising determining whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs, wherein the determining comprises:
measuring a first value of leakage current between the electrically conductive chain and a silicon substrate of the multi-layer semiconductor structure before forming the one or more TSVs;
measuring a second value of leakage current between the electrically conductive chain and the silicon substrate of the multi-layer semiconductor structure after forming the one or more TSVs; and
detecting existence of the damage when the second value of leakage current is different than the first value of leakage current.

### Claim 59 (depends on 55)

A method as recited in claim 55, wherein forming the electrically conductive chain comprises:
forming a plurality of metal lines; and
forming a plurality of vias each of which coupling respective two of the plurality of metal lines such that the plurality of metal lines are electrically coupled in series forming a series resistor.

### Claim 60 (depends on 55)

A method as recited in claim 55, wherein forming the electrically conductive chain includes forming a plurality of metal lines, wherein the plurality of metal lines are coupled in a staircase-like matter such that the plurality of metal lines are embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 61 (depends on 55)

A method as recited in claim 55 further comprising:
forming a guard ring that is embedded in the multi-layer semiconductor structure, between the one or more TSVs and the electrically conductive chain, and encompassing the one or more TSVs.

### Claim 62 (depends on 55)

A method as recited in claim 55, further comprising forming a guard ring, wherein forming the guard ring comprises:
forming a continuous line of metal embedded in a first layer of the multi-layer semiconductor structure; and
forming a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 63 (depends on 55)

A method as recited in claim 55, further comprising forming a guard ring, wherein the guard ring comprises:
forming a continuous line of dielectric embedded in a first layer of the multi-layer semiconductor structure; and
forming a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 64 (depends on 55)

A method as recited in claim 55, further comprising forming a guard ring, wherein the guard ring is embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 65 (depends on 55)

A method as recited in claim 55, further comprising forming a guard ring, wherein the guard ring hermetically seals the one or more TSVs such that moisture and contaminants related to fabrication of the TSVs are prevented from diffusing outside of the guard ring.

### Claim 66

A method comprising:
providing a multi-layer semiconductor structure;
forming a guard ring that is embedded in the multi-layer semiconductor structure and encompassing a through-silicon via region of the multi-layer semiconductor structure; and
forming one or more through-silicon vias (TSVs) that traverse through the through-silicon via region of the multi-layer semiconductor structure.

### Claim 67 (depends on 66)

A method as recited in claim 66, wherein forming the guard ring comprises:
forming a continuous line of metal embedded in a first layer of the multi-layer semiconductor structure; and
forming a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 68 (depends on 66)

A method as recited in claim 66, wherein forming the guard ring comprises:
forming a continuous line of dielectric embedded in a first layer of the multi-layer semiconductor structure; and
forming a continuous line of via embedded in a second layer of the multi-layer semiconductor structure adjacent the first layer.

### Claim 69 (depends on 66)

A method as recited in claim 66, wherein the guard ring is embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.

### Claim 70 (depends on 66)

A method as recited in claim 66, wherein the guard ring hermetically seals the one or more TSVs such that moisture and contaminants related to fabrication of the TSVs are prevented from diffusing outside of the guard ring.

### Claim 71 (depends on 66)

A method as recited in claim 66 further comprising:
forming an electrically conductive chain embedded in the multi-layer semiconductor structure around the guard ring before forming the one or more TSVs.

### Claim 72 (depends on 66)

A method as recited in claim 66 further comprising:
determining, based on an electrical property related to the electrically conductive chain, whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs.

### Claim 73 (depends on 66)

A method as recited in claim 66, further comprising determining whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs, wherein the determining comprises:
measuring a first resistive value of the electrically conductive chain before forming the one or more TSVs;
measuring a second resistive value of the electrically conductive chain after forming the one or more TSVs; and
detecting damage to a portion of the multi-layer semiconductor structure induced during a process of forming the TSVs when the second resistive value is different than the first resistive value.

### Claim 74 (depends on 66)

A method as recited in claim 66, further comprising determining whether damage to a portion of the multi-layer semiconductor structure was induced during a process of forming the TSVs, wherein the determining comprises:
measuring a first value of leakage current between the electrically conductive chain and the Guard ring or a silicon substrate of the multi-layer semiconductor structure before forming the one or more TSVs;
measuring a second value of leakage current between the electrically conductive chain and the Guard ring or the silicon substrate of the multi-layer semiconductor structure after forming the one or more TSVs; and
detecting damage to a portion of the multi-layer semiconductor structure induced during a process of forming the TSVs when the second value of leakage current is different than the first value of leakage current.

### Claim 75 (depends on 66)

A method as recited in claim 66, further comprising forming an electrically conductive chain, wherein forming the electrically conductive chain comprises:
forming a plurality of metal lines; and
forming a plurality of vias each of which coupling respective two of the plurality of metal lines such that the plurality of metal lines are electrically coupled in series forming a series resistor.

### Claim 76 (depends on 66)

A method as recited in claim 66, further comprising forming a plurality of metal lines, wherein the plurality of metal lines are coupled in a staircase-like matter such that the plurality of metal lines are embedded in each layer of the multi-layer semiconductor structure through which the one or more TSVs are fabricated.