# US 2014/0191408 A1 · Backside metal ground plane with improved metal adhesion and design structures

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- Number: US 2014/0191408 A1
- Document ID: US20140191408A1
- Status: Published application
- Kind: A1
- Application number: 13/738,541
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jay S. BURNHAM; Damyon L. CORBIN; George A. DUNBAR, III; Jeffrey P. GAMBINO; John C. HALL; Kenneth F. MCAVEY, JR.; Charles F. MUSANTE; Anthony K. STAMPER
- Web page: https://patentgrep.com/patent/US20140191408A1

## CPC

- H10W 70/635: {Through-vias}
- G06F 30/00: Computer-aided design [CAD]
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

## Claims

### Claim 1

A method comprising:
forming at least one through silicon via (TSV) in a substrate;
forming an oxide layer on a backside of the substrate; and
forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the metalized ground plane eliminates peeling when the substrate is diced.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the metalized ground plane comprises depositing a metal on a backside of the wafer, in direct contact with the at least one TSV and the oxide layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the forming the at least one TSV comprises a polishing and grinding process of the substrate, which forms the oxide layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the forming the oxide layer comprises a Si etch using a wet chemistry of hydrogen peroxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the oxide layer comprises an oxide deposition process using oxygen plasma.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the oxide layer comprises a low temperature thermal oxidation process at 100° C., in air.

### Claim 8 (depends on 1)

The method of claim 1, further comprising cleaning impurities from exposed portions of the at least one TSV, using a low energy Ar sputter process.

### Claim 9 (depends on 8)

The method of claim 8, wherein the low energy Ar sputter process has an energy level of less than or equal to about 3E14 cm−2.

### Claim 10 (depends on 1)

The method of claim 1, wherein the oxide layer forms a recessed portion, exposing a metal of the at least one TSV.

### Claim 11 (depends on 1)

The method of claim 1, wherein the forming the at least one TSV forms a recessed portion of the substrate, adjacent to the at least one TSV.

### Claim 12 (depends on 1)

The method of claim 1, wherein the forming the at least one TSV forms a planar or substantially planar surface with an exposed portion of the at least one TSV and the oxide layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the oxide layer is SiOx, where x is between 1 and 2.

### Claim 14

A method comprising:
forming a plurality of through silicon vias (TSVs) in a substrate, comprising:
forming openings partially within the substrate;
filling the openings with a metal; and
thinning the substrate to expose a backside of the metal within the via, such that the metal via extends entirely through the substrate, wherein the thinning process results in an oxide layer formed on a backside of the substrate; and
forming a backside metal on the oxide layer such that the backside metal is in direct contact with the plurality of TSVs and the oxide layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the oxide layer is SiOx, where x is between 1 and 2.

### Claim 16 (depends on 14)

The method of claim 14, wherein:
the forming the backside metal comprises depositing a metal on a backside of the substrate; and
the thinning of the substrate comprises a Si etch using a wet chemistry of hydrogen peroxide.

### Claim 17 (depends on 14)

The method of claim 14, wherein the forming the oxide layer is further formed by an oxide deposition process using oxygen plasma.

### Claim 18 (depends on 14)

The method of claim 14, wherein the oxide layer is further formed by a low temperature thermal oxidation process at 100° C., in air.

### Claim 19 (depends on 14)

The method of claim 14, further comprising cleaning impurities from exposed portions of the plurality of TSVs, using a low energy Ar sputter process.

### Claim 20 (depends on 19)

The method of claim 19, wherein the low energy Ar sputter process has an energy level of less than or equal to about 3E14 cm−2.

### Claim 21 (depends on 14)

The method of claim 14, wherein the backside metal is planar.

### Claim 22 (depends on 21)

The method of claim 21, wherein the backside metal is planarized using a chemical mechanical polish.

### Claim 23 (depends on 14)

The method of claim 14, further comprising:
dicing the substrate to form a plurality of chips, each of which include at least one of the TSVs and the backside metal; and
bonding at least one of the plurality of chips to a substrate by the backside metal.

### Claim 24

A structure, comprising:
a substrate comprising at least one through silicon via extending entirely through the substrate;
an oxide layer on a backside of the substrate; and
a metalized ground plane on a backside of the substrate, directly in contact with metal of the at least one through silicon via and the oxide layer on the backside.

### Claim 25

A method in a computer-aided design system for generating a functional design model of a structure with a backside metal, the method comprising:
generating a functional representation of a substrate comprising at least one through silicon via extending entirely through the substrate;
generating a functional representation of an oxide layer on a backside of the substrate; and
generating a functional representation of a metalized ground plane on a backside of the substrate, directly in contact with metal of the at least one through silicon via and the oxide layer on the backside.