# US 2014/0191407 A1 · Dielectric posts in metal layers

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- Number: US 2014/0191407 A1
- Document ID: US20140191407A1
- Status: Published application
- Kind: A1
- Application number: 13/737,957
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Globalfoundries Singapore Pte. Ltd.
- Inventors: Fan ZHANG; Wei SHAO; Juan Boon TAN; Yeow Kheng LIM; Mahesh BHATKAR; Soh Yun SIAH
- Web page: https://patentgrep.com/patent/US20140191407A1

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 20/43: Layouts of interconnections
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate comprises a plurality of metal layers; and
dielectric posts disposed in the metal layers, wherein the density of the dielectric posts in the metal layers is equal to about 15-25%.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 further comprising via bar disposed in between adjacent metal layers.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein the metal layers are disposed in a crack stop region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3 wherein the via bar comprises a mesh design or a straight line design.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the metal layers comprise wide metal lines.

### Claim 6 (depends on 5)

The semiconductor device of claim 5 wherein the wide metal lines are about 4.5-7 μm wide.

### Claim 7 (depends on 5)

The semiconductor device of claim 5 wherein the wide metal lines are wider than about 7 μm wide.

### Claim 8 (depends on 5)

The semiconductor device of claim 5 wherein the dielectric posts comprise a dielectric material.

### Claim 9 (depends on 8)

The semiconductor device of claim 8 wherein the dielectric posts extend the thickness of the wide metal lines.

### Claim 10 (depends on 9)

The semiconductor device of claim 9 wherein the dielectric posts do not come into contact with the via bars above and below the wide metal lines.

### Claim 11

A semiconductor device comprising:
a substrate comprises a plurality of metal levels having metal layers disposed in a crack stop region; and
dielectric posts disposed in the metal layers, wherein the density of the dielectric posts in the metal layers is equal to about 15-25%.

### Claim 12 (depends on 11)

The semiconductor device of claim 11 further comprising via levels disposed in between adjacent metal levels.

### Claim 13 (depends on 12)

The semiconductor device of claim 12 wherein via bars are disposed in the via levels.

### Claim 14 (depends on 13)

The semiconductor device of claim 13 wherein the via bars comprise a mesh design or straight line design.

### Claim 15 (depends on 14)

The semiconductor device of claim 14 wherein the metal layers comprise wide metal lines.

### Claim 16 (depends on 15)

The semiconductor device of claim 15 wherein the wide metal lines are about 4.5-7 μm wide.

### Claim 17 (depends on 16)

The semiconductor device of claim 16 wherein the dielectric posts comprise a dielectric material.

### Claim 18 (depends on 17)

The semiconductor device of claim 17 wherein the dielectric posts extend the thickness of the wide metal lines.

### Claim 19 (depends on 18)

The semiconductor device of claim 18 wherein the dielectric posts do not come into contact with the via bars above and below the wide metal lines.

### Claim 20

A semiconductor device comprising:
a substrate prepared with circuit components formed thereon, the substrate having a crack-stop region disposed in a peripheral region of the circuit components;
a plurality of metal layers disposed in the crack-stop region; and
dielectric posts disposed in the metal layers, wherein the density of the dielectric posts in the metal layers is equal to about 15-25%.