# US 2014/0191406 A1 · Manufacturing method for semiconductor package, semiconductor package, and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191406 A1 - Document ID: US20140191406A1 - Status: Published application - Kind: A1 - Application number: 14/235,766 - Filed: 2012-10-18 - Published: 2014-07-10 - Earliest claimed: 2011-10-19 - Assignees: Panasonic Corporation - Applicants: Panasonic Corporation - Inventors: Hiromitsu Takashita; Tsuyoshi Takeda; Keiko Kashihara; Hiroaki Fujiwara; Shingo Yoshioka - Web page: https://patentgrep.com/patent/US20140191406A1 ## CPC - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/0198: {batch processes} - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/655: Fan-out layouts - H10W 70/68: Shapes or dispositions thereof - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/01921: {using local deposition} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01955: {by using masks} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/9413: {on encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated. ## Claims ### Claim 1 A manufacturing method for a semiconductor package comprising: a covering step of forming a covering insulating layer that covers a surface of a semiconductor element on which electrodes are formed, the semiconductor element including the electrodes on a principal plane thereof; a film-forming step of forming a resin film on a surface of the covering insulating layer on the electrodes side of the semiconductor element; a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching surfaces of the electrodes and a circuit groove having a desired shape and a desired depth, by applying laser processing or embossing to the covering insulating layer from an outer surface side of the resin film; a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on a surface of the circuit pattern portion and a surface of the resin film; a film-separating step of separating the resin film from the covering insulating layer; and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated. ### Claim 2 (depends on 1) The manufacturing method for a semiconductor package according to claim 1, wherein the covering step is a step of embedding the semiconductor element in the covering insulating layer. ### Claim 3 (depends on 2) The manufacturing method for a semiconductor package according to claim 2, wherein the covering step includes: a bonding step of bonding at least one or more of the semiconductor elements in a predetermined position of a supporting body to which the semiconductor elements are detachably attached; a sealing resin-covering step of covering the semiconductor elements bonded to the supporting body with sealing resin such that the semiconductor elements are embedded; a hardening step of hardening the sealing resin and forming a first insulating layer; a supporting body-separating step of separating the supporting body from the semiconductor elements and the first insulating layer; and a second insulating layer-forming step of forming a second insulating layer on surfaces of the semiconductor elements and the first insulating layer with which the supporting body is in contact to thereby form the covering insulating layer including the first insulating layer and the second insulating layer. ### Claim 4 (depends on 3) The manufacturing method for a semiconductor package according to claim 3, wherein the supporting body includes a base material and a layer which is provided on at least one surface of the base material and to which the semiconductor elements are detachably attached, and the layer to which the semiconductor elements are detachably attached is an adhesive layer made of silicone resin. ### Claim 5 (depends on 2) The manufacturing method for a semiconductor package according to claim 2, wherein the covering step includes: a bonding step of bonding at least one or more of the semiconductor elements in a predetermined position of a third insulating layer of a supporting body including a base material and the third insulating layer which is provided on at least one surface of the base material and to which the semiconductor elements can be fixed; a sealing resin-covering step of covering the semiconductor elements bonded to the supporting body with sealing resin such that the semiconductor elements are embedded; a hardening step of hardening the sealing resin and forming a fourth insulating layer to thereby form the covering insulating layer including the third insulating layer and the fourth insulating layer; and a base material-separating step of separating the base material from the third insulating layer. ### Claim 6 (depends on 3) The manufacturing method for a semiconductor package according to claim 3, wherein the sealing resin is a resin sheet or a resin film including hardening resin and an inorganic filler. ### Claim 7 (depends on 1) The manufacturing method for a semiconductor package according to claim 1, wherein the covering step includes forming, as the covering insulating layer, a covering insulating layer such that a surface of the semiconductor element on an opposite side to the electrodes is exposed. ### Claim 8 (depends on 7) The manufacturing method for a semiconductor package according to claim 7, wherein the covering step includes: a sticking step of sticking at least one or more of the semiconductor elements to a supporting body such that surfaces of the semiconductor elements on an opposite side to the electrodes come into contact with predetermined positions of the supporting body; a sealing resin-covering step of covering, with sealing resin, the surfaces on which the electrodes are formed of the semiconductor elements stuck to the supporting body; and a hardening step of hardening the sealing resin and forming the covering insulating layer. ### Claim 9 (depends on 8) The manufacturing method for a semiconductor package according to claim 8, wherein the supporting body is a supporting body to which the semiconductor elements are detachably attached, and the manufacturing method further comprises, after the covering step, a supporting body-separating step of separating the supporting body. ### Claim 10 (depends on 9) The manufacturing method for a semiconductor package according to claim 9, wherein the supporting body includes a base material and a layer which is provided on at least one surface of the base material and to which the semiconductor elements are detachably attached, and the layer to which the semiconductor elements are detachably attached is an adhesive layer made of silicone resin. ### Claim 11 (depends on 8) The manufacturing method for a semiconductor package according to claim 8, wherein the sealing resin is a resin sheet or a resin film including hardening resin and an inorganic filler. ### Claim 12 (depends on 1) The manufacturing method for a semiconductor package according to claim 1, wherein the covering step includes forming a covering insulating layer having projections of a predetermined shape on the surface of the semiconductor element on the electrodes side, and the circuit pattern-forming step includes forming, as the circuit groove, a circuit groove reaching surfaces of the projections and coupled to the recesses. ### Claim 13 (depends on 12) The manufacturing method for a semiconductor package according to claim 12, wherein the covering step includes: a fifth insulating layer-forming step of forming a fifth insulating layer on a surface of a supporting body including recesses corresponding to the projections; a sticking step of sticking at least one or more of the semiconductor elements to the fifth insulating layer such that the surfaces of the semiconductor elements on which the electrodes are formed come into contact with the fifth insulating layer; a sealing resin-covering step of covering the semiconductor elements stuck to the fifth insulating layer with sealing resin such that the semiconductor elements are embedded; a hardening step of hardening the sealing resin and forming a sixth insulating layer to thereby form the covering insulating layer including the fifth insulating layer and the sixth insulating layer; and a supporting body-separating step of separating the supporting body from the covering insulating layer. ### Claim 14 (depends on 13) The manufacturing method for a semiconductor package according to claim 13, wherein the sealing resin is a resin sheet or a resin film including hardening resin and an inorganic filler. ### Claim 15 (depends on 12) The manufacturing method for a semiconductor package according to claim 12, further comprising a step of forming solder bumps on the circuit formed on the projections. ### Claim 16 (depends on 1) The manufacturing method for a semiconductor package according to claim 1, wherein the circuit includes a circuit formed, with respect to the surface of the covering insulating layer, on an outer side of an outer edge of a shape of the semiconductor element projected in a direction orthogonal to the principal plane of the semiconductor element. ### Claim 17 (depends on 1) A semiconductor package obtained by the manufacturing method for a semiconductor package according to claim 1. ### Claim 18 (depends on 17) A semiconductor device, comprising: the semiconductor package according to claim 17; and one or more wiring layers including circuits electrically connected to the circuit of the semiconductor package. ### Claim 19 (depends on 5) The manufacturing method for a semiconductor package according to claim 5, wherein the sealing resin is a resin sheet or a resin film including hardening resin and an inorganic filler.