# US 2014/0191405 A1 · Method of forming patterns for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191405 A1 - Document ID: US20140191405A1 - Status: Published application - Kind: A1 - Application number: 14/208,456 - Filed: 2014-03-13 - Published: 2014-07-10 - Earliest claimed: 2009-02-27 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Young-Ho Lee; Jae-Hwang Sim; Sang-Yong Park; Kyung-Lyul Moon - Web page: https://patentgrep.com/patent/US20140191405A1 ## CPC - H10W 20/43: Layouts of interconnections - H10B 41/10: characterised by the top-view layout - H10B 41/40: characterised by the peripheral circuit region - H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask} - H10P 50/696: {Process specially adapted to improve the resolution of the mask} - H10P 50/73: {using masks for insulating materials} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10P 76/4088: {Processes for improving the resolution of the masks} - H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/315: {with the capacitor higher than a bit line} - H10W 20/031: {of conductive parts of the interconnections} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of bit lines disposed on a substrate, the plurality of bit lines extending parallel to each other in a first direction and being spaced apart from each other in a second direction perpendicular to the first direction; and a first pair of node-separated bit lines interposed between two neighboring bit lines selected from the plurality of bit lines, the first pair of node-separated bit lines being lined up in the first direction and being spaced apart from each other in the first direction with a separation region on the substrate therebetween. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first pair of node-separated bit lines have different lengths from each other in the first direction. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the two neighboring bit lines are spaced apart from each other in the second direction by the separation region. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first pair of node-separated bit lines and the separation region are interposed between the two neighboring bit lines. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the plurality of bit lines and the first pair of node-separated bit lines are arranged at equal intervals in the second direction in a metallization region surrounding the separation region on the substrate. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein at least one bit line of the two neighboring bit lines has a protruding portion extending from a sidewall of the at least one bit line toward the separation region. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising a contact pad formed on the separation region and integrally connected to the two neighboring bit lines, wherein each of the first pair of node-separated bit lines is spaced apart from the contact pad. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising: a second pair of node-separated bit lines interposed between the two neighboring bit lines, the second pair of node-separated bit lines being lined up in the first direction and being spaced apart from each other in the first direction with the separation region therebetween. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first pair of node-separated bit lines are spaced apart from each other in the first direction by a first distance, and the second pair of node-separated bit lines are spaced apart from each other in the first direction by a second distance, the second distance being different from the first distance. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein the first pair of node-separated bit lines have different lengths from each other in the first direction, wherein the second pair of node-separated bit lines have different lengths from each other in the first direction, and wherein the length of the first pair of node-separated bit lines is different from the length of the second pair of node-separated bit lines in the first direction. ### Claim 11 A semiconductor device comprising: a plurality of bit lines extending parallel to each other in a first direction on a substrate, the plurality of bit lines including a first group of bit lines space apart from each other in a second direction perpendicular to the first direction by a first distance, and a second group of bit lines space apart from each other in the second direction by the first distance; and at least one pair of node-separated bit lines extending in the first direction between the first group of bit lines and the second group of bit lines, the at least one pair of node-separated bit lines having a first node-separated bit line and a second node-separated bit line lined up in the first direction and being spaced apart from each other in the first direction with a separation region on the substrate therebetween, wherein the first node-separated bit line and the second node-separated bit line have different lengths from each other in the first direction. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein at least one bit line selected from the first group of bit lines and the second group of bit lines has a protruding portion extending from a sidewall of the selected bit line toward the separation region. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the first group of bit lines includes a first bit line having a first protruding portion extending from a sidewall of the first bit line toward the separation region, and wherein the second group of bit lines includes a second bit line having a second protruding portion extending from a sidewall of the second bit line toward the separation region. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the first protruding portion and the second protruding portion are face to face with each other. ### Claim 15 (depends on 11) The semiconductor device of claim 11, further comprising a contact pad formed on the separation region and integrally connected to a first bit line selected from the first group of bit lines and to a second bit line selected from the second group of bit lines, wherein each node-separated bit line of the at least one pair of node-separated bit lines is spaced apart from the contact pad.