# US 2014/0191403 A1 · Multi-die semiconductor package and method of manufacturing thereof

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- Number: US 2014/0191403 A1
- Document ID: US20140191403A1
- Status: Published application
- Kind: A1
- Application number: 13/735,272
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: LSI Corporation
- Applicants: Lsi Corporation
- Inventors: Ivor G. Barber
- Web page: https://patentgrep.com/patent/US20140191403A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/63: Vias, e.g. via plugs
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of the first die, (3) a second die coupled to the substrate, the second die having a second set of terminals and bearing a second IC that substantially occupies an area of the second die, the first and second ICS being mirror-images of one another and (4) interconnects coupling corresponding terminals of the first and second sets together.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate;
a first die coupled to said substrate, said first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of said first die;
a second die coupled to said substrate, said second die having a second set of terminals and bearing a second IC that substantially occupies an area of said second die, said first and second ICS being mirror-images of one another; and
interconnects coupling corresponding terminals of said first and second sets together.

### Claim 2 (depends on 1)

The semiconductor package as recited in claim 1 wherein said interconnects are substantially parallel.

### Claim 3 (depends on 1)

The semiconductor package as recited in claim 1 wherein said interconnects lie outside of said areas of said first and second ICs.

### Claim 4 (depends on 1)

The semiconductor package as recited in claim 1 wherein said multi-chip module is in a format selected from the group consisting of:
a multi-chip module format,
a 2.5D format, and
a SoC format.

### Claim 5 (depends on 1)

The semiconductor package as recited in claim 1 wherein said first and second die have further sets of terminals located along other edges thereof.

### Claim 6 (depends on 1)

The semiconductor package as recited in claim 1 wherein said first and second edges are substantially parallel and side-by-side with one another.

### Claim 7 (depends on 1)

The semiconductor package as recited in claim 1 wherein said interconnects are located on or in said substrate.

### Claim 8

A method of manufacturing a semiconductor package, comprising:
coupling a first die to a substrate, said first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of said first die;
coupling a second die to said substrate, said second die having a second set of terminals and bearing a second IC that substantially occupies an area of said second die, said first and second ICS being mirror-images of one another, interconnects coupling corresponding terminals of said first and second sets together.

### Claim 9 (depends on 8)

The method as recited in claim 8 wherein said interconnects are substantially parallel.

### Claim 10 (depends on 8)

The method as recited in claim 8 wherein said interconnects lie outside of said areas of said first and second ICs.

### Claim 11 (depends on 8)

The method as recited in claim 8 wherein said semiconductor package is in a format selected from the group consisting of:
a multi-chip module,
a 2.5D format, and
a SoC format.

### Claim 12 (depends on 8)

The method as recited in claim 8 wherein said first and second die have further sets of terminals located along other edges thereof.

### Claim 13 (depends on 8)

The method as recited in claim 8 wherein said first and second edges are substantially parallel and side-by-side with one another.

### Claim 14 (depends on 8)

The method as recited in claim 8, further comprising forming said interconnects on or in said substrate.

### Claim 15

A method of manufacturing a semiconductor package, comprising:
creating an integrated circuit (IC) design;
creating a first layout of said design that has multiple layers;
creating a second layout of said design that is a mirror image of said first layout, corresponding ones of said multiple layers of said first and second layouts being mirror images of one another;
employing said first layout to fabricate a first die;
employing said second layout to fabricate a second die; and
collocating said first and second dies in said semiconductor package.

### Claim 16 (depends on 15)

The method as recited in claim 15 wherein said creating said second layout comprises creating a mirror image of each of said multiple layers of said first layout.

### Claim 17 (depends on 15)

The method as recited in claim 15 wherein said employing said first layout comprises employing said layout and a wafer to fabricate a plurality of first dies.

### Claim 18 (depends on 15)

The method as recited in claim 15 wherein said employing said first layout and said employing said second layout are carried concurrently using a single set of reticles.

### Claim 19 (depends on 15)

The method as recited in claim 15 further comprising forming substantially parallel interconnects between a first set of terminals located along a first edge of said first die and a second edge of said second die.

### Claim 20 (depends on 15)

The method as recited in claim 15 wherein said semiconductor package is in a format selected from the group consisting of:
a multi-chip module,
a 2.5D format, and
a SoC format.