# US 2014/0191402 A1 · Barrier Layer for Copper Interconnect

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- Number: US 2014/0191402 A1
- Document ID: US20140191402A1
- Status: Published application
- Kind: A1
- Application number: 14/204,347
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2012-11-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Hung Lin; Chi-Yu Chou; Kuei-Pin Lee; Chen-Kuang Lien; Yu-Chang Hsiao; Yao-Hsiang Liang; Yu-Min Chang
- Web page: https://patentgrep.com/patent/US20140191402A1

## CPC

- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/44: Conductive materials thereof
- H10W 20/4424: {Copper alloys}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer.

## Claims

### Claim 1

A device, comprising:
a dielectric layer overlying a substrate;
a conductive line with a sidewall in the dielectric layer;
a Ta layer adjoining the sidewall of the conductive line; and
a metal oxide between the Ta layer and the dielectric layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the Ta layer has an α phase, BCC structure.

### Claim 3 (depends on 1)

The device of claim 1, wherein the metal oxide is MnOx, TiOx, AlOx, CoOx, VOx, YOx, TcOx, ReOx, or combinations thereof.

### Claim 4 (depends on 1)

The device of claim 1, further comprising a CuMn layer formed between the metal oxide and the Ta layer.

### Claim 5

A device, comprising:
a dielectric layer overlying a substrate;
an opening in the dielectric layer;
a metal-containing layer overlying the opening;
a barrier layer overlying the metal-containing layer;
a conductive layer in the opening; and
a metal oxide barrier layer underlying the conductive layer.

### Claim 6 (depends on 5)

The device of claim 5, wherein the barrier layer has a resistivity less than about 60 μΩ/cm.

### Claim 7 (depends on 5)

The device of claim 5, wherein the metal-containing layer has a crystal structure of face center cubic (FCC) structure.

### Claim 8 (depends on 5)

The device of claim 5, wherein the barrier layer has a crystal structure of body center cubic (BCC) structure.

### Claim 9 (depends on 5)

The device of claim 5, wherein the metal-containing layer is a CuMn layer, a CuNb layer, a CuTi layer, a CuAl layer, a CuCo layer, a CuV layer, a CuY layer, a CuTc layer, a CuRe, or combinations thereof.

### Claim 10 (depends on 5)

The device of claim 5, wherein the metal-containing layer is Cu-containing layer.

### Claim 11 (depends on 10)

The device of claim 10, wherein the Cu-containing layer comprises an additive metal element including manganese (Mn), aluminum (Al), titanium (Ti), niobium (Nb), chromium (Cr), vanadium (V), yttrium (Y), technetium (Tc), rhenium (Re), cobalt (Co), or combinations thereof.

### Claim 12 (depends on 5)

The device of claim 5, wherein the barrier layer is a tantalum (Ta) layer.

### Claim 13 (depends on 12)

The device of claim 12, wherein the tantalum layer is an α phase tantalum layer (α-Ta) layer.

### Claim 14 (depends on 5)

The device of claim 5, wherein the metal oxide barrier layer is MnOx and/or MnSiyOz.

### Claim 15 (depends on 5)

The device of claim 5, wherein a combined thickness of the metal-containing layer and the barrier layer is less than about 120 angstroms.

### Claim 16

A device, comprising:
a dielectric layer overlying a substrate;
a recess cavity in the dielectric layer;
a CuMn layer overlying the recess cavity;
a α phase tantalum layer overlying the CuMn layer within the recess cavity;
a conductive layer overlying the α phase tantalum layer within the recess cavity; and
a MnOx barrier layer underlying the conductive layer.

### Claim 17 (depends on 16)

The device of claim 16, wherein the CuMn layer has a thickness less than about 150 angstroms.

### Claim 18 (depends on 16)

The device of claim 16, wherein an etch stop layer is disposed between the dielectric layer and the substrate, and wherein the recess cavity extends into the etch stop layer.

### Claim 19 (depends on 16)

The device of claim 16, wherein the recess cavity includes an upper trench section above a lower trench section, the upper trench section having a width greater than the lower trench section.

### Claim 20 (depends on 16)

The device of claim 16, wherein the α phase tantalum layer has a resistivity less than about 60 μΩ/cm.

### Claim 21 (depends on 16)

The device of claim 16, wherein the CuMn layer has a thickness ranging from about 5 angstroms to about 50 angstroms.

### Claim 22 (depends on 16)

The device of claim 16, wherein the CuMn layer has a crystal structure.