# US 2014/0191401 A1 · Airgap interconnect with hood layer and method of formiing

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- Number: US 2014/0191401 A1
- Document ID: US20140191401A1
- Status: Published application
- Kind: A1
- Application number: 13/997,171
- Filed: 2011-12-29
- Published: 2014-07-10
- Earliest claimed: 2011-12-29
- Assignees: Intel Corporation
- Inventors: Kevin Fischer
- Web page: https://patentgrep.com/patent/US20140191401A1

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having a dielectric layer with a plurality of interconnects formed therein, wherein each interconnect has a top surface and a side surface;
an airgap located between adjacent interconnects; and
a plurality of hood layers, wherein each hood layer contacts at least a portion of each of the top surface and the side surface of one of the adjacent interconnects.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the hood layer is selected from the group consisting of Co and Co alloys.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the hood layer is 5-15 nm thick.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the adjacent interconnects are copper.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a gap-sealing dielectric layer above the hood layer, wherein the gap-sealing dielectric layer seals the airgap.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a barrier layer covering a portion of the side surface of each interconnect.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the barrier layer is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, and ruthenium.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a conformal liner layer, wherein the conformal liner layer conforms to the top surface of the hood layer, the interface between the hood layer and the airgap, and the interface between the airgap and the dielectric layer.

### Claim 9

A method for forming a semiconductor device comprising:
providing a substrate having a dielectric layer with a plurality of interconnects formed therein, wherein each interconnect has a top surface and a side surface;
forming a hardmask on the dielectric layer and patterning the hardmask to expose the dielectric layer surface between adjacent interconnects;
etching the dielectric layer between the two adjacent interconnects to form a trench, wherein the etching process exposes at least a portion of the side surface of each adjacent interconnect; and
electrolessly plating a hood layer onto the exposed portion of the top surface and the exposed portion of each side surface.

### Claim 10 (depends on 9)

The method of claim 9, wherein the trench is etched to a depth below the bottom edge of the adjacent interconnects.

### Claim 11 (depends on 9)

The method of claim 9, wherein the trench is etched to a depth above the bottom edge of the adjacent interconnects.

### Claim 12 (depends on 9)

The method of claim 9, wherein the hood layer is selected from the group consisting of Co and Co alloys.

### Claim 13 (depends on 9)

The method of claim 9, wherein the hood layer is 5-15 nm thick.

### Claim 14 (depends on 9)

The method of claim 9, wherein the adjacent interconnects are copper.

### Claim 15 (depends on 9)

The method of claim 9, further comprising:
forming a barrier layer on the side surface; and
etching at least a portion of the bather layer to expose the side surface.

### Claim 16 (depends on 15)

The method of claim 15, wherein the barrier layer is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, and ruthenium.

### Claim 17 (depends on 9)

The method of claim 9, further comprising forming a gap-sealing dielectric layer above the trench, wherein the gap-sealing dielectric layer seals the trench to form an airgap.

### Claim 18 (depends on 9)

The method of claim 9, further comprising forming a conformal liner layer, wherein the conformal liner layer conforms to the top surface of the hood layer and the edges of the trench.

### Claim 19

A method for forming a semiconductor device, comprising:
providing a substrate having a dielectric layer with a plurality of copper interconnects formed therein, wherein each copper interconnect has a top surface and a side surface, and wherein the side surface is covered by a barrier layer;
forming a hardmask on the dielectric layer;
patterning the hardmask to expose a portion of the surface of the dielectric layer between adjacent copper interconnects;
etching the dielectric layer between the adjacent copper interconnects to form a trench, wherein the etching process etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect;
electrolessly plating a cobalt hood layer onto an exposed portion of the top surface and the exposed portion of each side surface;
forming a gap-sealing dielectric layer over the hardmask, the cobalt hood layer and the trench, wherein the gap-sealing dielectric layer seals the trench to form an airgap.