# US 2014/0191394 A1 · Bumps for Chip Scale Packaging

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- Number: US 2014/0191394 A1
- Document ID: US20140191394A1
- Status: Published application
- Kind: A1
- Application number: 14/204,659
- Filed: 2014-03-11
- Published: 2014-07-10
- Earliest claimed: 2011-11-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Hung Lin; Yu-Feng Chen; Tsung-Shu Lin; Han-Ping Pu; Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US20140191394A1

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9232: {with additional elements interposed between layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

## Claims

### Claim 1

A device comprising:
a semiconductor die;
a first under bump metal structure formed in a first region of the semiconductor die, wherein the first under bump metal structure is of a first diameter;
a second under bump metal structure formed in a second region of the semiconductor die, wherein the second under bump metal structure is of a second diameter;
a first bump formed over the first under bump metal structure; and
a second bump formed over the second under bump metal structure.

### Claim 2 (depends on 1)

The device of claim 1, wherein:
the first region is an outer region of the semiconductor die;
the second region is an inner region of the semiconductor die; and
the first diameter is greater than the second diameter.

### Claim 3 (depends on 2)

The device of claim 2, wherein:
the outer region has a width approximately equal to or less than one third of a width of the inner region.

### Claim 4 (depends on 2)

The device of claim 2, wherein:
the second diameter is less than or equal to 90% of the first diameter.

### Claim 5 (depends on 1)

The device of claim 1, wherein:
the first bump is formed of solder; and
the second bump is formed of solder.

### Claim 6 (depends on 1)

The device of claim 1, wherein:
the first bump is of an hourglass shape.

### Claim 7 (depends on 1)

The device of claim 1, wherein:
the second bump has a diameter greater than a diameter of the first bump.

### Claim 8

A device comprising:
a semiconductor die;
a first under bump metal structure formed adjacent to an edge of the semiconductor die; and
a second under bump metal structure formed not adjacent to the edge of the semiconductor die, wherein the first under bump metal structure has a diameter greater than a diameter of the second under bump metal structure.

### Claim 9 (depends on 8)

The device of claim 8, further comprising:
a first bump formed over the first under bump metal structure; and
a second bump formed over the second under bump metal structure.

### Claim 10 (depends on 9)

The device of claim 9, wherein:
the second bump has a diameter greater than a diameter of the first bump.

### Claim 11 (depends on 9)

The device of claim 9, wherein:
the first bump is of an hourglass shape; and
the second bump is of a spherical shape.

### Claim 12 (depends on 8)

The device of claim 8, wherein:
the first under bump metal structure is formed on an outer region of the semiconductor die; and
the second under bump metal structure is formed on an inner region of the semiconductor die.

### Claim 13 (depends on 12)

The device of claim 12, wherein:
the outer region has a width approximately equal to or less than one third of a width of the inner region.

### Claim 14 (depends on 8)

The device of claim 8, wherein the semiconductor die comprises:
a substrate;
an interlayer dielectric layer formed on the substrate;
a plurality of metallization layers formed over the interlayer dielectric layer;
a passivation layer formed over the plurality of metallization layers; and
a polymer layer formed on the passivation layer, wherein a redistribution layer is formed in the polymer layer.

### Claim 15

A structure comprising:
a semiconductor die;
a first under bump metal structure having a first diameter formed on an outer region of the semiconductor die; and
a second under bump metal structure having a second diameter formed on an inner region of the semiconductor die, wherein the first under bump metal structure is different from the second under bump metal structure.

### Claim 16 (depends on 15)

The structure of claim 15, wherein the second diameter is greater than the first diameter.

### Claim 17 (depends on 15)

The structure of claim 15, wherein the outer region has a width approximately equal to or less than one third of a width of the inner region.

### Claim 18 (depends on 15)

The structure of claim 15, further comprising:
a first bump formed on the first under bump metal structure; and
a second bump formed on the second under metal structure.

### Claim 19 (depends on 18)

The structure of claim 18, wherein:
the first bump is thinner than the second bump; and
the first bump is of an hourglass shape.

### Claim 20 (depends on 15)

The structure of claim 15, wherein the semiconductor die comprises:
a substrate;
an interlayer dielectric layer formed on the substrate;
a plurality of metallization layers formed over the interlayer dielectric layer;
a passivation layer formed over the plurality of metallization layers; and
a polymer layer formed on the passivation layer, wherein a redistribution layer is formed in the polymer layer.