# US 2014/0191391 A1 · Elongated bump structures in package structure

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- Number: US 2014/0191391 A1
- Document ID: US20140191391A1
- Status: Published application
- Kind: A1
- Application number: 13/735,750
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yao-Chun Chuang; Chita Chuang; Ming Hung Tseng; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US20140191391A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.

## Claims

### Claim 1

A package structure, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar; and
a substrate comprising a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region,
wherein the chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region,
wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis; and
wherein L is greater than d1, and W is less than d2.

### Claim 2 (depends on 1)

The package structure of claim 1, further comprising a solder joint region between the conductive pillar and the pad region.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the mask layer is formed of a solder resist material layer.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the conductive pillar comprises copper or copper alloy.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the difference between L and d1 is greater than 20 μm.

### Claim 8 (depends on 1)

The package structure of claim 1, wherein the difference between d2 and W is greater than 2 μm.

### Claim 9 (depends on 1)

The package structure of claim 1, wherein d1 is substantially equal to d2.

### Claim 10

A package structure, comprising:
a chip comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar; and
a substrate comprising a mask layer overlying the substrate and having an opening, and a conductive region filling the opening of the mask layer and protruding from the top surface of the mask layer;
wherein the chip is attached to the substrate to form an interconnection between the conductive pillar and the conductive region,
wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis; and
wherein L is greater than d1, and W is less than d2.

### Claim 11 (depends on 10)

The package structure of claim 10, further comprising a solder joint region between the conductive pillar and the conductive region.

### Claim 12 (depends on 10)

The package structure of claim 10, wherein the mask layer is formed of a solder resist material layer.

### Claim 13 (depends on 10)

The package structure of claim 10, wherein the conductive pillar comprises copper or copper alloy.

### Claim 14 (depends on 10)

The package structure of claim 10, wherein the long axis of the conductive pillar is perpendicular to an edge of the chip.

### Claim 15 (depends on 10)

The package structure of claim 10, wherein the long axis of the conductive pillar is along a direction toward a central area of the chip.

### Claim 16 (depends on 10)

The package structure of claim 10, wherein the difference between L and d1 is greater than 20 μm.

### Claim 17 (depends on 10)

The package structure of claim 10, wherein the difference between d2 and W is greater than 2 μm.

### Claim 18 (depends on 10)

The package structure of claim 10, wherein d1 is substantially equal to d2.

### Claim 19

A method of forming a package structure, comprising:
forming a bump structure on a semiconductor substrate, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar;
forming a solder resist layer on a package substrate which having a pad region,
forming an opening in the solder resist layer, wherein the opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis, and wherein L is greater than d1, and W is less than d2; and
attaching a chip to the package substrate to form an interconnection between the conductive pillar and the pad region.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming a solder layer on at least one of the conductive pillar and the pad region.