# US 2014/0191389 A1 · Semiconductor device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191389 A1 - Document ID: US20140191389A1 - Status: Published application - Kind: A1 - Application number: 13/845,446 - Filed: 2013-03-18 - Published: 2014-07-10 - Earliest claimed: 2013-01-07 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Ki Hong LEE; Seung Ho PYI; Seok Min JEON - Web page: https://patentgrep.com/patent/US20140191389A1 ## CPC - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10D 88/00: Three-dimensional [3D] integrated devices - H10P 14/412: {Deposition of metallic or metal-silicide materials} - H10P 14/6314: {of a metallic layer} - H10P 30/40: into insulating materials - H10P 50/283: {by chemical means} - H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate in which a cell region and a contact region are defined; a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the plurality of first conductive layers are formed in a side region of the pad structure. ### Claim 3 (depends on 2) The semiconductor device of claim 2, further comprising a plurality of sacrificial layers coupled to the plurality of first conductive layers and formed in a central region of the pad structure. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the pad portions have a greater thickness than the plurality of sacrificial layers. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein each step of the pad structure includes one of the first conductive layers and a first insulating layer formed above the first conductive layer. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein each step of the pad structure includes one of the first conductive layers and a first insulating layer formed under the first conductive layer. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising a plurality of barrier layers formed on side walls of the plurality of pad portions. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising a buffer layer formed on an entire surface of the pad structure. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising a barrier layer formed on an entire surface of the pad structure. ### Claim 10 (depends on 1) The semiconductor device of claim 1, further comprising a plurality of contact plugs, wherein each of the plurality of contact plugs is coupled to each of the pad portions. ### Claim 11 (depends on 1) The semiconductor device of claim 1, further comprising: a cell structure coupled to the pad structure and including a plurality of second conductive layers and a plurality of second insulating layers formed alternately with each other in the cell region of the substrate; and a plurality of channel layers penetrating the cell structure. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the plurality of channel layers are formed in a U-shape or vertical shape manner. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the first and second conductive layers formed on the same level are coupled to each other, and the first and second insulating layers formed on the same level are coupled to each other. ### Claim 14 A semiconductor device, comprising: a substrate; a plurality of stacked structures including a plurality of conductive layers and a plurality of insulating layers formed alternately with each other on the substrate, wherein each end of the plurality of stacked structures is patterned stepwise; and at least one slit separating the plurality of stacked structures from each other, wherein portions of the plurality of conductive layers exposed at each end of the plurality of stacked structures are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of conductive layers. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the plurality of conductive layers are formed in a side region of the stacked structure. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein each of the stacked structures comprises a plurality of sacrificial layers coupled to the plurality of conductive layers and formed in a central region of the stacked structure. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the pad portions have a greater thickness than the plurality of sacrificial layers. ### Claim 18 (depends on 14) The semiconductor device of claim 14, further comprising a plurality of barrier layers formed on side walls of the plurality of pad portions. ### Claim 19 (depends on 14) The semiconductor device of claim 14, further comprising a buffer layer formed on an entire surface of the stacked structure. ### Claim 20 (depends on 14) The semiconductor device of claim 14, further comprising a barrier layer formed on an entire surface of the stacked structure.