# US 2014/0191387 A1 · Method of fabricating land grid array semiconductor package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0191387 A1
- Document ID: US20140191387A1
- Status: Published application
- Kind: A1
- Application number: 14/177,146
- Filed: 2014-02-10
- Published: 2014-07-10
- Earliest claimed: 2011-11-02
- Assignees: STMicroelectronics (Grenoble 2) SAS; Stmicroelectronics Pte Ltd
- Applicants: STMicroelectronics Pte Ltd.; STMicroelectronics Grenoble 2 SAS
- Inventors: Yonggang JIN; Romain COFFY; Jerome TEYSSEYRE
- Web page: https://patentgrep.com/patent/US20140191387A1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/10: Arrangements for heating
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T 29/49174: Assembling terminal to elongated conductor
- Y10T 29/49204: Contact or terminal manufacturing
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

## Claims

### Claim 1

A semiconductor package, comprising:
a portion of a reconstituted wafer, including a molding compound layer and a semiconductor die having a plurality of circuit pads positioned on a face of the semiconductor die, the semiconductor die being substantially embedded in the molding compound layer with the face of the semiconductor die lying coplanar with a face of the molding compound layer; and
a redistribution layer positioned on the face of the portion of the reconstituted wafer and having:
a plurality of electrical traces in electrical contact with respective ones of the plurality of circuit pads,
a plurality of contact lands defined on a face of the wafer portion, each electrically coupled to a respective one of the plurality of circuit pads via a corresponding one of the plurality of electrical traces, and
a heat spreader positioned over the semiconductor die and lying in a same layer of the redistribution layer as the plurality of electrical traces, the heat spreader being electrically isolated from the semiconductor die and substantially covering a majority of the face of the semiconductor die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1 wherein the redistribution layer further comprises:
a first dielectric layer positioned on the face of the portion of the reconstituted wafer between the portion of the reconstituted wafer and the layer that includes the plurality of electrical traces and the heat spreader, the first dielectric layer having a plurality of openings positioned over respective ones of the plurality of circuit pads, through which the electrical traces are coupled with respective ones of the plurality of circuit pads; and
a second dielectric layer positioned over the layer that includes the plurality of electrical traces and the heat spreader and having a plurality of openings positioned over respective ones of the plurality of electrical traces; and wherein
the plurality of contact lands comprises a layer of conductive material positioned in each of the plurality of openings in the second dielectric layer.

### Claim 3 (depends on 1)

The semiconductor package of claim 1 wherein the redistribution layer further comprises:
a first dielectric layer positioned on the face of the portion of the reconstituted wafer between the portion of the reconstituted wafer and the layer that includes the plurality of electrical traces and the heat spreader, the first dielectric layer having a plurality of openings positioned over respective ones of the plurality of circuit pads, through which the electrical traces are coupled with respective ones of the plurality of circuit pads;
a layer of metal deposited directly on, and substantially covering each of the plurality of electrical traces; and
a second dielectric layer positioned over the layer that includes the plurality of electrical traces and the heat spreader, and over the layer of metal; and wherein
the plurality of contact lands comprises a plurality of openings positioned over respective ones of the plurality of electrical traces, each exposing a portion of the layer of metal on the respective one of the plurality of electrical traces.

### Claim 4 (depends on 1)

The semiconductor package of claim 1 wherein the plurality of electrical traces is a first plurality of electrical traces, positioned in a first layer of the redistribution layer, and a portion of the heat spreader lies in a second layer of the redistribution layer, the device further comprising a second plurality of electrical traces positioned in the second layer of the redistribution layer.

### Claim 5 (depends on 1)

The semiconductor package of claim 1 wherein the redistribution layer further comprises a dielectric layer deposited on the layer having the plurality of electrical traces and the heat spreader, the dielectric layer including a window in which a portion of the heat spreader is exposed.

### Claim 6 (depends on 1)

The semiconductor package of claim 1 wherein the heat spreader has a first surface, the first surface having a first area, and wherein the face of the semiconductor die has a second area, the first area being smaller than the second area.

### Claim 7 (depends on 1)

The semiconductor package of claim 1 wherein the heat spreader covers approximately 80% or more of the semiconductor die.

### Claim 8

A device, comprising:
a first insulation layer;
a first metal layer over the first insulation layer, the first metal layer including:
a first electrical trace and a second electrical trace, the first electrical trace having a first end and a second end, the second electrical trace having a first end and a second end, the first and second electrical traces penetrating the first insulation layer at the first ends of the first and second electrical traces respectively, a first distance between the first ends of the first and second electrical traces being smaller than a second distance between the second ends of the first and second electrical traces; and
a heat spreader positioned between and electrically isolated from the first electrical trace and the second electrical trace;
a second insulation layer over the metal layer, the second insulation layer having an opening that exposes the heat spreader; and
a second metal layer over the second insulation layer, the second metal layer including a first contact land and a second contract land, the first contact land being coupled to the second end of the first electrical trace, and the second contact land being coupled to the second end of the second electrical trace.

### Claim 9 (depends on 8)

The device of claim 8 wherein a first surface has a first area that includes the first ends of the first and second electrical traces but excludes the second ends of the first and second electrical traces and wherein a second surface has a second area that includes both the first and the second ends of the first and second electrical traces, the second surface completely covering the first surface, the heat spreader constituting a third area that overlies the first area in part, the third area being bigger that the first area, and smaller than the second area.

### Claim 10 (depends on 9)

The device of claim 9 wherein the third area is substantially rectangular and the first and second area are substantially square.

### Claim 11 (depends on 8)

The device of claim 8 further comprising a portion of a reconstituted wafer, the first insulation layer overlying the portion of reconstituted wafer and the portion of reconstituted wafer including:
a molding compound; and
a semiconductor die, a surface of the semiconductor die flush with a surface of the portion of reconstituted wafer, the semiconductor die having a first contact pad on the surface of the semiconductor die flush with the surface of the portion of the reconstituted wafer, the first contact pad coupled to the first end of the first electrical trace.

### Claim 12 (depends on 11)

The device of claim 11 wherein the semiconductor die includes a second contact pad on the surface of the semiconductor die flush with the surface of the portion of the reconstituted wafer, the second contact pad couple to a first end of the second electrical trace.

### Claim 13 (depends on 8)

The device of claim 8 further comprising:
a metallic heat sink coupled to the heat spreader through the opening in the second insulation layer, the metallic heat sink extending away from the first insulation layer and passing through the opening in the second insulation layer, the metallic heat sink electrically isolated from the second metal layer.

### Claim 14 (depends on 8)

The device of claim 8 wherein the heat spreader is copper and the first and second contact lands comprise a first layer of nickel having a first thickness covered by a second layer of gold having a second thickness, the second thickness being smaller than the first thickness.

### Claim 15 (depends on 8)

The device of claim 8 wherein the heat spreader is electrically coupled to ground.

### Claim 16

A circuit, comprising:
a semiconductor die, the semiconductor die having a first surface and a plurality of contact pads on the first surface, the plurality of contact pads covering less than a majority of the first surface, the first surface having a first length and a first width; and
a molding compound encapsulating the semiconductor die on sides of the semiconductor die and a surface opposite the first surface; and
a redistribution level, the redistribution level directly on the first surface and coupled to the semiconductor die, the redistribution level having a second surface, the second surface having a second length and a second width in which the second length is greater than the first length and the second width is greater than the first width, the redistribution level including a heat sink overlying a majority of the first surface, the heat sink not overlying the plurality of contact pads on the first surface.

### Claim 17 (depends on 16)

The circuit of claim 16 wherein the redistribution level includes:
a plurality of contact lands, the plurality of contact lands not overlying the first surface, and
a plurality of signal lines, the plurality of signal lines configured to electrically couple respective ones of the plurality of contact pads to respective ones of the plurality of contact lands.

### Claim 18 (depends on 17)

The circuit of claim 17 wherein the plurality of signal lines and the heat sink are formed in the same metal layer, the heat sink and the plurality of signal lines electrically isolated from one another.

### Claim 19 (depends on 16)

The circuit of claim 16 wherein the redistribution level further comprises:
a first insulation layer, the insulation layer covering the first surface;
a metal layer, the metal layer over the insulation layer and the metal layer including the heat sink; and
a second insulation layer, the second insulation layer over the metal layer, the heat sink substantially exposed through the second insulation layer.

### Claim 20 (depends on 16)

The circuit of claim 16 wherein the heat sink comprises a majority of the second surface.