# US 2014/0191386 A1 · Semiconductor package and fabrication method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191386 A1 - Document ID: US20140191386A1 - Status: Published application - Kind: A1 - Application number: 13/894,716 - Filed: 2013-05-15 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Siliconware Precision Industries Co., Ltd. - Applicants: Siliconware Precision Industries Co., Ltd. - Inventors: Mei-Chin Lee; Wang-Ting Chen; Chi-Tung Yeh; Chun-Tang Lin; Yi-Che Lai - Web page: https://patentgrep.com/patent/US20140191386A1 ## CPC - H10W 40/253: {Semiconductors} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate; a semiconductor element having an active surface and an inactive surface opposing to the active surface and disposed on the substrate via the active surface, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. ### Claim 2 (depends on 1) The package of claim 1, wherein the active surface of the semiconductor element has a plurality of electrode pads electrically connected to the substrate. ### Claim 3 (depends on 1) The package of claim 1, wherein the thermally conductive layer is made of a low melting point thermally conductive material. ### Claim 4 (depends on 3) The package of claim 3, wherein the thermally conductive layer is made of a solder material. ### Claim 5 (depends on 1) The package of claim 1, wherein the thermally conductive layer comprises indium (In). ### Claim 6 (depends on 1) The package of claim 1, wherein the thermally conductive layer comprises 99.99% of indium (In) by weight. ### Claim 7 (depends on 1) The package of claim 1, wherein the thermally conductive layer has a melting point lower than 170° C. ### Claim 8 (depends on 1) The package of claim 1, further comprising a stiffener disposed on the substrate for supporting the heat sink. ### Claim 9 A fabrication method of a semiconductor package, comprising the steps of: disposing a semiconductor element on a substrate, wherein the semiconductor element has opposite active and inactive surfaces and is disposed on the substrate via the active surface thereof, and the inactive surface of the semiconductor element is roughened; and disposing a heat sink on the inactive surface of the semiconductor element via a thermally conductive layer. ### Claim 10 (depends on 9) The method of claim 9, wherein the step of disposing the semiconductor element on the substrate comprises: providing a semiconductor substrate having a plurality of semiconductor elements; cutting the semiconductor substrate to separate the semiconductor elements from each other; disposing at least one of the semiconductor elements on the substrate; and performing a surface treatment process to an inactive surface of the semiconductor element to form a roughened surface. ### Claim 11 (depends on 9) The method of claim 9, wherein the step of disposing the semiconductor element on the substrate comprises: providing a semiconductor substrate having a plurality of semiconductor elements; performing a surface treatment process to an inactive surface of the semiconductor substrate to form a roughened surface; cutting the semiconductor substrate to separate the semiconductor elements with the roughened surface from each other; and disposing at least one of the semiconductor elements on the substrate. ### Claim 12 (depends on 9) The method of claim 9, wherein the inactive surface of the semiconductor element is roughened through a surface process by using plasma. ### Claim 13 (depends on 9) The method of claim 9, wherein the step of disposing the heat sink on the inactive surface of the semiconductor element via the thermally conductive layer comprises: forming the thermally conductive layer on the inactive surface of the semiconductor element; and disposing the heat sink on the thermally conductive layer. ### Claim 14 (depends on 9) The method of claim 9, wherein the step of disposing the heat sink on the inactive surface of the semiconductor element via the thermally conductive layer comprises: forming the thermally conductive layer on the heat sink; and disposing the heat sink on the inactive surface of the semiconductor element with the thermally conductive layer bonded to the inactive surface of the semiconductor element. ### Claim 15 (depends on 9) The method of claim 9, wherein the thermally conductive layer is laminated on the inactive surface of the semiconductor element. ### Claim 16 (depends on 9) The method of claim 9, wherein the active surface of the semiconductor element has a plurality of electrode pads electrically connected to the substrate. ### Claim 17 (depends on 9) The method of claim 9, wherein the thermally conductive layer is made of a thermally conductive material having a low melting point. ### Claim 18 (depends on 17) The method of claim 17, wherein the thermally conductive layer is made of a solder material. ### Claim 19 (depends on 9) The method of claim 9, wherein the thermally conductive layer comprises indium (In) ### Claim 20 (depends on 9) The method of claim 9, wherein the thermally conductive layer comprises 99.99% of indium (In) by weight. ### Claim 21 (depends on 9) The method of claim 9, wherein the thermally conductive layer has a melting point lower than 170° C. ### Claim 22 (depends on 9) The method of claim 9, further comprising reflowing the thermally conductive layer. ### Claim 23 (depends on 9) The method of claim 9, wherein the substrate further has a stiffener disposed thereon for supporting the heat sink.