# US 2014/0191378 A1 · Integrated circuit package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191378 A1 - Document ID: US20140191378A1 - Status: Published application - Kind: A1 - Application number: 13/734,246 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Han Meng@Eugene Lee Lee; Anis Fauzi Abdul Aziz; Yien Sien Khoo - Web page: https://patentgrep.com/patent/US20140191378A1 ## CPC - H10W 90/00: Package configurations - H10W 70/421: {Shapes or dispositions} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 70/461: {specially adapted for cooling} - H10W 70/468: {Circuit boards} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/016: {using moulds} - H10W 90/811: {Multiple chips on leadframes} - H10W 70/475: {Capacitors in combination with leadframes} - H10W 72/0198: {batch processes} - H10W 72/07234: {Using a reflow oven} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/07334: {Using a reflow oven} - H10W 72/07336: {Soldering or alloying} - H10W 72/07354: {changes in dispositions} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe. ## Claims ### Claim 1 An integrated circuit (IC) package comprising: a bottom leadframe; an interposer mounted on said bottom leadframe; a flipchip die mounted on said interposer; and a top leadframe electrically connected to said interposer. ### Claim 2 (depends on 1) The IC package of claim 1 further comprising at least one field-effect transistor (FET) mounted on said interposer. ### Claim 3 (depends on 2) The IC package of claim 2 wherein said top leadframe is electrically connected to said bottom leadframe and said at least one FET. ### Claim 4 (depends on 1) The IC package of claim 1 comprising at least one passive circuit device mounted on said top leadframe. ### Claim 5 (depends on 5) The IC package of claim 5 wherein said passive circuit device is electrically connected to said top leadframe. ### Claim 6 (depends on 5) The IC package of claim 5 comprising a molding layer covering said at least one passive circuit device and portions of said top and bottom leadframes. ### Claim 7 (depends on 1) The IC package of claim 1, said bottom leadframe comprising a central pad portion. ### Claim 8 (depends on 7) The IC package of claim 7, said interposer being mounted on said bottom leadframe central pad portion and having an interposer leadframe. ### Claim 9 (depends on 7) The IC package of claim 7, said top leadframe comprising a plurality of leads, at least one of said plurality of leads being connected to said interposer leadframe. ### Claim 10 (depends on 9) The IC package of claim 9 said flipchip die comprising a plurality of metal bumps, said metal bumps being connected to said interposer leadframe. ### Claim 11 (depends on 10) The IC package of claim 10, said at least one FET being connected to said interposer leadframe. ### Claim 12 (depends on 11) The IC package of claim 11 at least one of said plurality of leads on said top leadframe being connected to said at least on FET. ### Claim 13 (depends on 1) The IC package of claim 1, said top leadframe comprising a plurality of leads each having a double downset configuration. ### Claim 14 (depends on 13) The IC package of claim 13, each double downset configuration terminating in a metal tab portion. ### Claim 15 (depends on 14) The IC package of claim 14 each said tab portion being connected to one of said bottom leadframe and said interposer leadframe. ### Claim 16 (depends on 1) The IC package of claim 1 said top leadframe comprising a plurality of outwardly extending lead portions, said bottom leadframe comprising a bottom surface, and further comprising a molding layer covering portions of said top and bottom leadframes, wherein said outwardly extending lead portions and said bottom surface of said bottom leadframe are exposed. ### Claim 17 An integrated circuit (IC) package comprising: a pad with a top surface and a bottom surface; an interposer comprising an interposer leadframe and having a top surface and a bottom surface, said interposer leadframe having a plurality of inner pad portions and a plurality of outer pad portions provided thereon, said outer pad portions being integrally connected to said inner pad portions, said bottom surface of said interposer being attached to said top surface of said pad, at least one field-effect transistor (FET) overlying and electrically connected to at least one of said outer pad portions of said patterned metal layer; a flipchip die having a first surface and an opposite second surface, said second surface having a plurality of solder bumps extending therefrom that are connected to said plurality of inner pad portions of said interposer leadframe; a top leadframe having a top surface and a bottom surface and having a plurality of lead portions with inner ends and outer ends, wherein at least one of said lead portions is connected at said inner end thereof to at least one of said outer pad portions of said interposer leadframe and wherein at least one of said lead portions is connected at said inner end thereof to said at least one FET; wherein said bottom leadframe is soldered to said top leadframe; at least one passive circuit device mounted on said top surface of said top leadframe and electrically connected to at least one of said lead portions of said top leadframe; and a mold compound covering said at least one passive circuit device and portions of said top and bottom leadframes and exposing outer portions of said lead portions and exposing a bottom surface of said pad. ### Claim 18 A method of making an integrated circuit (IC) package comprising: electrically and physically attaching a die to an interposer leadframe; attaching the interposer leadframe to a bottom leadframe; attaching a first circuit component to the interposer leadframe; and attaching a top leadframe to the bottom leadframe. ### Claim 19 (depends on 14) The method of claim 14 comprising attaching the top leadframe to the interposer leadframe with a lead portion having a double downset. ### Claim 20 (depends on 18) The method of claim 18 comprising attaching a passive circuit component to the top leadframe; and covering the top and bottom leadframes, except for portions of leads of the top leadframe and a portion of the bottom leadframe to which the interposer leadframe is attached, with mold compound.