# US 2014/0191372 A1 · Spacer assisted pitch division lithography

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- Number: US 2014/0191372 A1
- Document ID: US20140191372A1
- Status: Published application
- Kind: A1
- Application number: 13/976,077
- Filed: 2011-12-29
- Published: 2014-07-10
- Earliest claimed: 2011-12-29
- Assignees: Intel Corporation
- Inventors: Swaminathan Sivakumar; Elliot N. Tan
- Web page: https://patentgrep.com/patent/US20140191372A1

## CPC

- H10P 14/3451: {Structure}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- Y10S 438/942: Masking
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method for fabricating an integrated circuit, comprising:
providing a variable pitch backbone pattern on a substrate, the pattern having two or more line widths and two or more space widths;
depositing a conformal layer of spacer material on the pattern and substrate, wherein the conformal layer has a thickness of 1×, and at least one of the space widths of the pattern is 2× or less and is filled with the spacer material; and
removing excess spacer material so as to reveal a top surface of the backbone pattern and to reveal a top surface of the substrate below space widths of the pattern that are greater than 2×, wherein spacer material having a thickness of 1× remains on sidewalls of the pattern, and space widths of the pattern that are 2× or less remain at least partially filled with the spacer material.

### Claim 22 (depends on 21)

The method of claim 21 further comprising:
removing backbone pattern material thereby leaving one or more backbone line voids having a first width and one or more other backbone line voids having a second width; and
depositing a first semiconductor material into the backbone line voids.

### Claim 23 (depends on 22)

The method of claim 22 further comprising:
planarizing the first semiconductor material to reveal the remaining spacer material.

### Claim 24 (depends on 22)

The method of claim 22 wherein the first semiconductor material is an insulator.

### Claim 25 (depends on 22)

The method of claim 22 wherein the first semiconductor material is a conductor.

### Claim 26 (depends on 22)

The method of claim 22 further comprising:
removing the remaining spacer material thereby leaving one or more spacer material line voids having a first width and one or more other spacer material line voids having a second width; and
depositing a second semiconductor material into the spacer material line voids.

### Claim 27 (depends on 26)

The method of claim 26 further comprising:
planarizing the second semiconductor material to reveal the first semiconductor material.

### Claim 28 (depends on 27)

The method of claim 27 wherein the second semiconductor material is an insulator.

### Claim 29 (depends on 27)

The method of claim 27 wherein the second semiconductor material is a conductor.

### Claim 30 (depends on 26)

The method of claim 26 wherein the first semiconductor material is an insulator and the second semiconductor material is a conductor.

### Claim 31 (depends on 26)

The method of claim 26 wherein the pattern has a minimum pitch that is halved at least once by carrying out the method, thereby providing a final minimum pitch.

### Claim 32 (depends on 31)

The method of claim 31 wherein the final minimum pitch is below the resolution limit of an exposure system being used to carry out the method.

### Claim 33 (depends on 21)

An integrated circuit fabricated using the method of claim 21.

### Claim 34 (depends on 33)

An electronic device comprising one or more of the integrated circuit of claim 33.

### Claim 35 (depends on 34)

The electronic device of claim 34, wherein the device comprises at least one of a memory circuit, a communication chip, a processor, and/or a computing system.

### Claim 36 (depends on 21)

A lithography system configured for carrying out the method of claim 21.

### Claim 37 (depends on 36)

The lithography system of claim 36 further comprising a mask for providing the variable pitch backbone pattern.

### Claim 38

A partially-formed integrated circuit, comprising:
a variable pitch backbone pattern on a substrate, the pattern having two or more line widths and two or more space widths;
a selectively provisioned conformal layer of spacer material on the pattern and substrate, wherein the conformal layer has a thickness of 1×, and at least one of the space widths of the pattern is 2× or less and is filled with the spacer material; and
wherein excess spacer material has been removed so as to reveal a top surface of the backbone pattern and to reveal a top surface of the substrate below space widths of the pattern that are greater than 2×, wherein spacer material having a thickness of 1× remains on sidewalls of the pattern, and space widths of the pattern that are 2× or less remain at least partially filled with the spacer material.

### Claim 39 (depends on 38)

The integrated circuit of claim 38 wherein backbone pattern material is removed thereby leaving one or more backbone line voids having a first width and one or more other backbone line voids having a second width, and a first semiconductor material is deposited into the backbone line voids.

### Claim 40 (depends on 39)

The integrated circuit of claim 39 wherein the remaining spacer material is removed thereby leaving one or more spacer material line voids having a first width and one or more other spacer material line voids having a second width, and a second semiconductor material is deposited into the spacer material line voids.