# US 2014/0191366 A1 · High-K and Metal Filled Trench-Type EDRAM Capacitor with Electrode Depth and Dimension Control

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- Number: US 2014/0191366 A1
- Document ID: US20140191366A1
- Status: Published application
- Kind: A1
- Application number: 13/738,170
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Colin J. Brodsky; Anne C. Friedman; Herbert Lei Ho; Byeong Yeol Kim; Dan Mihai Mocuta; Garrett W. Oakley; Chienfan Yu
- Web page: https://patentgrep.com/patent/US20140191366A1

## CPC

- H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/0387: {Making the trench}
- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10D 1/716: {having vertical extensions}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield.

## Claims

### Claim 1

A method of semiconductor device manufacture comprising steps of
forming an aperture in a layer of material extending over other material,
applying an organic planarizing layer (OPL) over a surface of said integrated circuit and within said apertures,
partially removing said OPL within said apertures to form OPL plugs in said apertures,
performing material removal steps around said apertures or OPL plugs,
removing said OPL plugs, and
performing additional processes on said electronic element.

### Claim 2 (depends on 1)

The method as recited in claim 1 wherein said aperture is formed above an electronic element.

### Claim 3 (depends on 2)

The method as recited in claim 2 wherein said electronic element is a storage node.

### Claim 4 (depends on 3)

The method as recited in claim 3 wherein said storage node is a capacitor.

### Claim 5 (depends on 4)

The method as recited in claim 4 wherein said capacitor is a deep trench capacitor.

### Claim 6 (depends on 1)

The method as recited in claim 1 wherein said semiconductor device includes a memory array.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein said step of removal of said OPL plugs includes etching having a lateral component.

### Claim 8 (depends on 1)

The method as recited in claim 1, wherein a material removal process prior to OPL plug removal is selective to said OPL material.

### Claim 9 (depends on 1)

The method as recited in claim 1 wherein said material removal process includes CHF4 or CF4 gas.

### Claim 10 (depends on 1)

The method as recited in claim 1 wherein OPL removal includes Hbr, O2 or CO2.

### Claim 11

A method of semiconductor device manufacture comprising steps of
forming an aperture in a layer of material extending over other material,
applying an organic planarizing layer (OPL) over a surface of said integrated circuit and within said apertures,
partially removing said OPL within said apertures,
performing a material removal operation,
removing said OPL material within said apertures, said step of removing OPL material including lateral etching of OPL material and other exposed material in said aperture, and
performing additional processes on said electronic element.

### Claim 12 (depends on 11)

The method as recited in claim 11 wherein said aperture is formed above an electronic element.

### Claim 13 (depends on 12)

The method as recited in claim 12 wherein said electronic element is a storage node.

### Claim 14 (depends on 12)

The method as recited in claim 12 wherein said electronic element is a deep trench capacitor.

### Claim 15 (depends on 11)

The method as recited in claim 11 wherein said semiconductor device includes a memory array.

### Claim 16 (depends on 11)

The method as recited in claim 11, wherein a material removal process prior to OPL plug removal is selective to said OPL material.

### Claim 17 (depends on 11)

The method as recited in claim 11 wherein said material removal process includes CHF4 or CF4 gas.

### Claim 18

A semiconductor wafer including
an electronic element formed below a surface of a substrate or layer of semiconductor material, and
a conductive body of material formed within an aperture and in contact with said electronic element wherein said conductive body of material is recessed substantially uniformly at all locations on said semiconductor wafer.

### Claim 19 (depends on 18)

The semiconductor wafer as recited in claim 18 wherein said electronic element is a deep trench capacitor.

### Claim 20

A semiconductor device including
two electronic elements formed below a surface of a substrate or layer of semiconductor material,
two conductive bodies of material formed within respective apertures and in contact with respective ones of said two electronic elements, and
a strap connection connecting said two conductive bodies wherein a width of said strap connection corresponds to a degree of overlay error in the location of said strap connection relative to said two conductive bodies.

### Claim 21 (depends on 20)

The semiconductor device as recited in claim 20 wherein said conductive bodies of material are recessed substantially uniformly at all locations of said semiconductor device.

### Claim 22 (depends on 21)

The semiconductor device as recited in claim 21 wherein one of said electronic elements is a deep trench capacitor