# US 2014/0191359 A1 · Semiconductor-on-oxide structure and method of forming

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- Number: US 2014/0191359 A1
- Document ID: US20140191359A1
- Status: Published application
- Kind: A1
- Application number: 14/151,550
- Filed: 2014-01-09
- Published: 2014-07-10
- Earliest claimed: 2012-03-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: John E. Barth, JR.; Herbert L. Ho; Babar A. Khan; Kirk D. Peterson
- Web page: https://patentgrep.com/patent/US20140191359A1

## CPC

- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

## Claims

### Claim 1

A semiconductor-on-oxide wafer comprising:
a substrate;
a first dielectric layer over the substrate;
a first conductive layer over the first dielectric layer;
a second dielectric layer over the first dielectric layer;
a second conductive layer over a portion of the second dielectric layer, the second conductive layer including a separation;
a third dielectric layer over the second conductive layer; and
a contact extending through the third dielectric layer and the separation in the second conductive layer contacting the first conductive layer.

### Claim 2 (depends on 1)

The wafer of claim 1, wherein the contact includes at least one of tungsten, copper or polysilicon.

### Claim 3 (depends on 1)

The wafer of claim 1, wherein the second conductive layer includes an additional separation, and the first conductive layer includes a separation aligned with the additional separation in the second conductive layer.

### Claim 4 (depends on 3)

The wafer of claim 3, further comprising a second contact extending through the additional separation in the second conductive layer and the separation in the first conductive layer.

### Claim 5 (depends on 4)

The wafer of claim 4, wherein the second contact contacts the substrate.

### Claim 6 (depends on 5)

The wafer of claim 5, wherein the second contact abuts an edge of a chip division in the wafer.

### Claim 7 (depends on 1)

The wafer of claim 1, further comprising a semiconductor isolation structure located entirely within the third dielectric layer.

### Claim 8 (depends on 7)

The wafer of claim 7, further comprising a plurality of contacts extending through the third dielectric layer contacting the second conductive layer, wherein the semiconductor isolation structure separates two of the plurality of contacts.

### Claim 9 (depends on 8)

The wafer of claim 8, wherein the second conductive layer includes tungsten or tungsten silicide.

### Claim 10

A semiconductor-on-oxide wafer comprising:
a substrate;
a first dielectric layer over the substrate;
a first conductive layer over the first dielectric layer;
a second dielectric layer over the first dielectric layer;
a second conductive layer over a portion of the second dielectric layer, the second conductive layer including a separation;
a third dielectric layer over the second conductive layer; and
an insulated contact extending through the third dielectric layer and the separation in the second conductive layer contacting one of the first conductive layer or the substrate, the insulated contact including a liner and a conductive material.

### Claim 11 (depends on 10)

The wafer of claim 10, wherein the liner contacts the second conductive layer and electrically insulates the conductive material from the second conductive layer.