# US 2014/0191358 A1 · Two-Portion Shallow-Trench Isolation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191358 A1 - Document ID: US20140191358A1 - Status: Published application - Kind: A1 - Application number: 13/736,082 - Filed: 2013-01-08 - Published: 2014-07-10 - Earliest claimed: 2013-01-08 - Assignees: United Microelectronics Corp. - Applicants: United Microelectronics Corp. - Inventors: En-Chiuan Liou; Po-Chao Tsao; Chia-Jui Liang; Jia-Rong Wu - Web page: https://patentgrep.com/patent/US20140191358A1 ## CPC - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/0147: {the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/834: {comprising FinFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled. ## Claims ### Claim 1 A shallow trench isolation structure, comprising: an upper insulating portion and a lower insulating portion in a trench of a substrate, wherein said lower insulating portion comprises a first insulator and an insulating layer on the sidewall and the bottom of said first insulator, said upper insulating portion comprises a second insulator and a buffer layer on the sidewall and the bottom of said second insulator, a part of said buffer layer interfaces between said first insulator and said second insulator, and the outer sidewall of said buffer layer and the sidewall of said first insulator are leveled. ### Claim 2 (depends on 1) A shallow trench isolation structure according to claim 1, wherein the material of said first insulator and said second insulator is silicon oxide. ### Claim 3 (depends on 1) A shallow trench isolation structure according to claim 1, wherein the material of said buffer layer comprises stress buffer film, silicon nitride, or silicon carbonitride. ### Claim 4 (depends on 1) A shallow trench isolation structure according to claim 1, wherein said shallow trench isolation structure is an isolating structure between fin field effect transistors. ### Claim 5 (depends on 1) A shallow trench isolation structure according to claim 1, wherein the top surface of said upper insulating portion is higher than the surface of said substrate. ### Claim 6 (depends on 1) A shallow trench isolation structure according to claim 1, further comprising a pad oxide layer and a hard mask layer formed on said substrate. ### Claim 7 A shallow trench isolation structure, comprising: an upper insulating portion and a lower insulating portion in a trench of a substrate, wherein said lower insulating portion comprises a first insulator and an insulating layer on the sidewall and the bottom of said first insulator, said upper insulating portion comprises a second insulator and a buffer layer on the sidewall of said second insulator, said first insulator and said second insulator are connected, and the outer sidewall of said buffer layer and the sidewall of said first insulator are leveled. ### Claim 8 (depends on 7) A shallow trench isolation structure according to claim 7, wherein the material of said buffer layer comprises stress buffer film, silicon nitride, or silicon carbonitride. ### Claim 9 (depends on 7) A shallow trench isolation structure according to claim 7, wherein the material of said first insulator and said second insulator is silicon oxide. ### Claim 10 (depends on 7) A shallow trench isolation structure according to claim 7, wherein said shallow trench isolation structure is an isolating structure between fin field effect transistors. ### Claim 11 (depends on 7) A shallow trench isolation structure according to claim 7, wherein the top surface of said upper insulating portion is higher than the surface of said substrate. ### Claim 12 (depends on 7) A shallow trench isolation structure according to claim 7, further comprising a pad oxide layer and a hard mask layer formed on said substrate. ### Claim 13 A method of forming shallow trench isolation structures, comprising the steps of: forming a trench in a substrate; filling a first insulating layer in the lower portion of said trench and defining a recess at the upper portion of said trench; forming a buffer layer on the sidewall of said recess; filling a second insulating layer in said recess; and performing a steam annealing process to transform said substrate surrounding said first insulating layer into an oxide layer. ### Claim 14 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, wherein said first insulating layer is filled into said trench by a flowable chemical vapor deposition process. ### Claim 15 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, further comprising the step of performing a chemical mechanical polishing process and/or an etch-back process on said first insulating layer to form said recess. ### Claim 16 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, further comprising the step of performing a chemical mechanical polishing process and/or an etch-back process on said second insulating layer, so that the top surface of said second insulating layer is lower than the surface of said substrate. ### Claim 17 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, wherein the step of forming said buffer layer on the sidewall of said recess comprises: forming said buffer layer conformally on said recess; and selectively removing said buffer layer on the bottom of said recess so that only said buffer layer on the sidewall of said recess remains. ### Claim 18 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, wherein said second insulator is filled in said recess by a sub-atmospheric chemical vapor deposition process or a flowable chemical vapor deposition process. ### Claim 19 (depends on 13) A method of forming shallow trench isolation structures according to claim 13, wherein said buffer layer transforms into an oxide layer through said steam annealing process.