# US 2014/0191352 A1 · Wafer-level packaging method of bsi image sensors having different cutting processes

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- Number: US 2014/0191352 A1
- Document ID: US20140191352A1
- Status: Published application
- Kind: A1
- Application number: 14/150,307
- Filed: 2014-01-08
- Published: 2014-07-10
- Earliest claimed: 2013-01-09
- Assignees: China Wafer Level CSP Co., Ltd.
- Applicants: China Wafer Level CSP Co., Ltd.
- Inventors: Zhi-Qi WANG; Qiong YU; Wei WANG
- Web page: https://patentgrep.com/patent/US20140191352A1

## CPC

- H10F 39/026: {Wafer-level processing}
- H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12}
- H10F 39/028: {performed after manufacture of the image sensors, e.g. annealing, gettering of impurities, short-circuit elimination or recrystallisation}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/804: {Containers or encapsulations}
- H10F 39/811: {Interconnections}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7416: {used during dicing or grinding}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.

## Claims

### Claim 1

A wafer-level packaging method of BSI image sensors comprising the following steps:
S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate, an image sensing region and a plurality of pads;
S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors;
S3: forming a first insulative layer on a outmost surface of the wafer package body; and
S4: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors; wherein
the first blade is wider than the second blade so that a cutting side of the BSI image sensor is of a step-shaped configuration, and the cutting side is sealed by the first insulative layer.

### Claim 2 (depends on 1)

The wafer-level packaging method as claimed in claim 1, wherein the first blade is a metallic blade and the second blade is a resin blade.

### Claim 3 (depends on 1)

The wafer-level packaging method as claimed in claim 1, wherein hardness of the first blade is greater than that of the second blade.

### Claim 4 (depends on 1)

The wafer-level packaging method as claimed in claim 1, further comprising the following steps before the step S2:
forming a plurality of pad grooves on the silicon base to expose the pads and a plurality of slots to expose the interconnect layer; and
forming a second insulative layer on a surface of the silicon base.

### Claim 5

A wafer-level packaging method of BSI image sensors comprising the following steps:
S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate, an image sensing region and a plurality of pads;
S2: cutting the wafer package body by laser in a first cutting process to separate the interconnect layers of adjacent BSI image sensors, and simultaneously forming V-shaped slots;
S3: forming a first insulative layer on a outmost surface of the wafer package body and the first insulative layer covers inner sides of the V-shaped slots; and
S4: cutting the wafer package body via a blade in a second cutting process to obtain independent BSI image sensors.

### Claim 6 (depends on 5)

The wafer-level packaging method as claimed in claim 5, wherein the blade is a resin blade.

### Claim 7 (depends on 5)

The wafer-level packaging method as claimed in claim 5, further comprising following steps before the step S2:
forming a plurality of pad grooves on the silicon base to expose the pads and a plurality of slots to expose the interconnect layer; and
forming a second insulative layer on a surface of the silicon base.

### Claim 8 (depends on 7)

The wafer-level packaging method as claimed in claim 7, wherein in the step S4, the blade cuts from the slots from a position between two scribe traces formed in the first cutting process to separate the BSI image sensors.

### Claim 9

A BSI image sensor packaging structure comprising:
a silicon base;
a transparent substrate;
an interconnect layer located between the silicon base and the transparent substrate, an image sensing region, a plurality of pads corresponding to the image sensing region and an interconnect-layer cross section exposed to the air; and
an insulative layer covering the interconnect-layer cross section; wherein
the BSI image sensor packaging structure comprises a sidewall which is of a step-shaped configuration, and the sidewall is sealed by the insulative layer.

### Claim 10 (depends on 9)

The BSI image sensor packaging structure as claimed in claim 9, further comprising a recess extending through the interconnect layer, the recess being located between the pads and the sidewall of the BSI image sensor packaging structure, the interconnect-layer cross section being formed on an inner side of the recess.

### Claim 11

A BSI image sensor packaging structure comprising:
a silicon base;
a transparent substrate;
an interconnect layer located between the silicon base and the transparent substrate, an image sensing region and a plurality of pads corresponding to the image sensing region, the interconnect layer comprising V-shaped slots; and
an insulative layer covering inner sides of the V-shaped slots; wherein
the interconnect layer connected with the pads is sealed by the silicon base, the transparent substrate and the insulative layer.

### Claim 12 (depends on 11)

The BSI image sensor packaging structure as claimed in claim 11, wherein the BSI image sensor packaging structure comprises a sidewall, and the sidewall further comprises a step which is covered by the insulative layer.

### Claim 13 (depends on 11)

The BSI image sensor packaging structure as claimed in claim 11, wherein the V-shaped slots are located between the pads and a sidewall of the BSI image sensor packaging structure.