# US 2014/0191347 A1 · Solid-state imaging device

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- Number: US 2014/0191347 A1
- Document ID: US20140191347A1
- Status: Published application
- Kind: A1
- Application number: 13/957,878
- Filed: 2013-08-02
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Jiro HAYAKAWA; Tomoyuki Yoda
- Web page: https://patentgrep.com/patent/US20140191347A1

## CPC

- H10F 77/20: Electrodes
- H10F 39/182: {Colour image sensors}
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/811: {Interconnections}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer.

## Claims

### Claim 1

A solid-state imaging device comprising:
a semiconductor substrate including a pixel area and a peripheral circuit area and having a first principal surface and a second principal surface;
an interconnection structure provided on the first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area;
a second interconnection layer provided in the peripheral circuit area and on the second principal surface of the semiconductor substrate;
a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween; and
through electrodes electrically connecting the second interconnection layer to the third interconnection layer and passing through the semiconductor substrate.

### Claim 2 (depends on 1)

The device of claim 1, wherein
the through electrodes include a first through electrode and a second through electrode,
the first through electrode electrically connects the second interconnection layer to the interconnection structure and passes through the semiconductor substrate, and
the second through electrode electrically connects the third interconnection layer to the interconnection structure and passes through the semiconductor substrate.

### Claim 3 (depends on 1)

The device of claim 1, wherein the second and third interconnection layers are each formed in the peripheral circuit area in a planar manner.

### Claim 4 (depends on 1)

The device of claim 1, further comprising a via plug electrically connecting the second interconnection layer to the third interconnection layer.

### Claim 5 (depends on 1)

The device of claim 1, wherein
the second interconnection layer includes first interconnection portions separated by a slit, and
the third interconnection layer includes second interconnection portions separated by a slit.

### Claim 6 (depends on 5)

The device of claim 5, wherein the slit of the third interconnection layer differs in location from the slit of the second interconnection layer in a planar view.

### Claim 7 (depends on 5)

The device of claim 5, wherein the second and third interconnection layers are formed to cover the peripheral circuit area.

### Claim 8 (depends on 1)

The device of claim 1, wherein the second and third interconnection layers are made of a light-shielding material.

### Claim 9 (depends on 1)

The device of claim 1, further comprising a light-shielding film formed in part of the pixel area and on the second principal surface of the semiconductor substrate,
wherein the second and third interconnection layers are made of a same material as that of the light-shielding film.

### Claim 10 (depends on 1)

The device of claim 1, wherein each of the second and third interconnection layers is one of a power line and a signal line.

### Claim 11 (depends on 2)

The device of claim 2, wherein
the second interconnection layer is a power line and is formed in the peripheral circuit area in a planar manner, and
the third interconnection layer is a signal line.

### Claim 12 (depends on 11)

The device of claim 11, wherein the first through electrode is provided near the second through electrode.

### Claim 13 (depends on 12)

The device of claim 12, wherein the first through electrode is formed to surround the second through electrode.

### Claim 14 (depends on 11)

The device of claim 11, further comprising a shield line formed to surround the third interconnection layer,
wherein the shield line is electrically connected to the second interconnection layer.

### Claim 15 (depends on 1)

The device of claim 1, further comprising light-receiving elements provided in the pixel area and on the second principal surface of the semiconductor substrate.