# US 2014/0191340 A1 · Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0191340 A1
- Document ID: US20140191340A1
- Status: Published application
- Kind: A1
- Application number: 13/738,147
- Filed: 2013-01-10
- Published: 2014-07-10
- Earliest claimed: 2013-01-10
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Deepak Thimmegowda; Andrew R. Bicksler; Roland Awusie
- Web page: https://patentgrep.com/patent/US20140191340A1

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/662: {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10P 14/40: of conductive or resistive materials
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

## Claims

### Claim 1

A transistor, comprising:
gate dielectric directly against a channel region;
a first conductive gate portion along a first segment of the channel region, and spaced from said first segment by at least the gate dielectric; and
a second conductive gate portion along a second segment of the channel region, and spaced from said second segment by at least the gate dielectric; the second segment being adjacent the first segment; the second conductive gate portion comprising a different composition from the first conductive gate portion and being directly against the first conductive gate portion.

### Claim 2 (depends on 1)

The transistor of claim 1 wherein the first and second conductive gate portions are directly against the gate dielectric.

### Claim 3 (depends on 1)

The transistor of claim 1 wherein the first and second conductive gate portions are directly against an electrically conductive material, which in turn is directly against the gate dielectric.

### Claim 4 (depends on 1)

The transistor of claim 1 wherein one of the first and second gate portions consists of conductively-doped semiconductor material and the other of the first and second gate portions comprises metal.

### Claim 5 (depends on 4)

The transistor of claim 4 wherein said one of the first and second gate portions consists of conductively-doped polysilicon.

### Claim 6 (depends on 4)

The transistor of claim 4 wherein said other of the first and second gate portions comprises metal nitride or metal silicide.

### Claim 7

A semiconductor construction, comprising:
a channel region;
gate dielectric directly against the channel region;
a semiconductor-containing gate portion along a first segment of the channel region and spaced from said first segment by at least the gate dielectric; the semiconductor-containing gate portion consisting of conductively-doped semiconductor material;
a metal-containing gate portion along a second segment of the channel region and spaced from said second segment by at least the gate dielectric; the second segment being adjacent the first segment; the metal-containing gate portion being directly against the semiconductor-containing gate portion; and
the semiconductor-containing gate portion, metal-containing gate portion, dielectric material and channel region comprising a transistor.

### Claim 8 (depends on 7)

The semiconductor construction of claim 7 wherein the metal-containing gate portion and the semiconductor-containing gate portion are both directly against the gate dielectric.

### Claim 9 (depends on 8)

The semiconductor construction of claim 8 wherein the metal-containing gate portion is a first metal-containing gate portion, and further comprising a second metal-containing gate portion directly against the gate dielectric and spaced from the first metal-containing gate portion by the semiconductor-containing gate portion.

### Claim 10 (depends on 8)

The semiconductor construction of claim 8 wherein the semiconductor-containing gate portion is a first semiconductor-containing gate portion, and further comprising a second semiconductor-containing gate portion directly against the gate dielectric and spaced from the first semiconductor-containing gate portion by the metal-containing gate portion.

### Claim 11 (depends on 7)

The semiconductor construction of claim 7 wherein the metal-containing gate portion and the semiconductor-containing gate portion are both directly against an electrically conductive material, which in turn is directly against the gate dielectric.

### Claim 12 (depends on 11)

The semiconductor construction of claim 11 wherein the metal-containing gate portion is a first metal-containing gate portion, and further comprising a second metal-containing gate portion directly against the electrically conductive material and spaced from the first metal-containing gate portion by the semiconductor-containing gate portion.

### Claim 13 (depends on 11)

The semiconductor construction of claim 11 wherein the semiconductor-containing gate portion is a first semiconductor-containing gate portion, and further comprising a second semiconductor-containing gate portion directly against the electrically conductive material and spaced from the first semiconductor-containing gate portion by the metal-containing gate portion.

### Claim 14

(canceled)

### Claim 15 (depends on 7)

The semiconductor construction of claim 7 wherein the metal-containing gate portion comprises metal silicide or metal nitride.

### Claim 16 (depends on 7)

The semiconductor construction of claim 7 wherein the semiconductor-containing gate portion consists of conductively-doped polysilicon.

### Claim 17 (depends on 7)

The semiconductor construction of claim 7 wherein the channel region is over such an upper surface of a base and extends substantially vertically relative to such upper surface.

### Claim 18 (depends on 17)

The semiconductor construction of claim 17 further comprising a NAND string, and wherein the transistor is electrically coupled with the NAND string.

### Claim 19 (depends on 18)

The semiconductor construction of claim 18 wherein:
the channel region is configured as a pillar laterally surrounded by the gate dielectric; and
the metal-containing gate portion and the semiconductor-containing gate portion entirely laterally surround said pillar; with the metal-containing gate portion being over the semiconductor-containing gate portion.

### Claim 20 (depends on 19)

The semiconductor construction of claim 19 wherein:
the semiconductor-containing gate portion consists of conductively-doped polysilicon; and
the metal-containing gate portion consists of titanium nitride or tungsten silicide.

### Claim at position 21

21-32. (canceled)