# US 2014/0191339 A1 · Semiconductor structures and fabrication method thereof

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- Number: US 2014/0191339 A1
- Document ID: US20140191339A1
- Status: Published application
- Kind: A1
- Application number: 13/919,276
- Filed: 2013-06-17
- Published: 2014-07-10
- Earliest claimed: 2013-01-08
- Assignees: Semiconductor Manufacturing International Corp.
- Applicants: Semiconductor Manufacturing International Corp.
- Inventors: ZHONGSHAN HONG
- Web page: https://patentgrep.com/patent/US20140191339A1

## CPC

- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate having a plurality of first doped regions and a plurality of second doped regions;
forming a first dielectric layer having a plurality of first openings and a plurality of second openings on the semiconductor substrate;
forming a first gate dielectric layer and a second dielectric layer in each of the first opening and each of second opening, respectively;
forming a first metal gate and a second metal gate on the first gate dielectric layer and the second dielectric layer, respectively;
forming a third dielectric layer on the second metal gate;
forming a second dielectric layer on the first dielectric layer, the third dielectric layers, and the first metal gates;
forming at least one fourth opening exposing at least one of the first metal gates and one of the first doped regions; and
forming a first contact layer electrically contacting with the first metal gate and the first doped region to be used as a share contact structure in the fourth opening.

### Claim 2 (depends on 1)

The method according claim 1, wherein forming at least one fourth opening further includes:
forming at least one fifth opening exposing at least one of the second doped regions at the same time when forming the fourth opening.

### Claim 3 (depends on 1)

The method according to claim 1, wherein forming a first contact layer further includes:
forming a second contact layer contacting with at least one of the second doped regions to be used as a self-aligned contact structure.

### Claim 4 (depends on 1)

The method according to claim 1, wherein forming the third dielectric layer further includes:
removing a top portion of the second metal gate; and
forming a third dielectric material layer on the remaining second metal gate.

### Claim 5 (depends on 1)

The method according to claim 1, after forming the second dielectric layer, further including:
forming a mask layer at least having a sixth opening exposing a position corresponding at least one first metal gate and at least one first doped region.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the first opening and the second openings further includes:
forming a plurality of adjacent first dummy gate structures and a plurality of adjacent second dummy gate structures on the semiconductor substrate;
forming the first doped regions in the semiconductor substrate at both sides of each of the first dummy gate structures and the second doped regions in the semiconductor substrate between any two adjacent second dummy gate structures;
forming the first dielectric layer; and
removing the first dummy gate structures to form the first openings and the second dummy gate structures to form the second openings.

### Claim 7 (depends on 1)

The method according to claim 1, before forming the first metal gate and second metal gate, further including:
forming a work function layer on the first gate dielectric layer and the second dielectric layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein forming the first contact layer further includes:
filling the fourth opening with a metal material; and
removing a portion of the metal material on the second dielectric layer to make the surface of the metal material inside the fourth opening level with the surface of the second dielectric layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
the first contact layer is made of titanium or tungsten;
the first gate dielectric layer and the second gate dielectric layer are made of high dielectric constant material;
the first dielectric layer and the second dielectric layer are made of one of silicon oxide and low dielectric constant material;
the first metal gate and the second metal gate are made of copper, tungsten, aluminum, or silver; and
the third dielectric layer is made of silicon nitride.

### Claim 10 (depends on 6)

The method according to claim 6, before forming the first dielectric layer, further including:
forming a barrier layer on the surface of the semiconductor substrate, sidewalls of the first dummy gate structures and the second dummy gate structures.

### Claim 11 (depends on 9)

The method according to claim 9, wherein:
the portion of the metal material on the second dielectric is removed by a chemical mechanical polishing process.

### Claim 12

A semiconductor structure, comprising:
a semiconductor substrate having a plurality of first doped regions and a plurality of second doped regions;
a first dielectric layer on the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
at least one first gate dielectric layer on the semiconductor substrate;
a first metal gate on the first gate dielectric layer;
a plurality of second gate dielectric layers;
a second metal gate on each of the second gate dielectric layers;
a third dielectric layer on the second metal gate; and
a first contact layer electrically contacting with the first metal gate and the first doped region simultaneously,
wherein the first contact layer is formed by:
forming an opening to expose at least one first metal gate and at least one first doped region; and
filling the fourth opening with a metal material.

### Claim 13 (depends on 12)

The semiconductor structure according to claim 12, wherein:
the first contact layer is isolated with the second metal gate, and used as a share contact structure.

### Claim 14 (depends on 12)

The semiconductor structure according to claim 12, wherein:
a barrier layer is formed between the first dielectric layer and the semiconductor substrate.

### Claim 15 (depends on 12)

The semiconductor structure according to claim 12, wherein:
sidewall spacers are formed on the semiconductor substrate at both sides of the first gate dielectric layers and the second gate dielectric layers.

### Claim 16 (depends on 12)

The semiconductor structure according to claim 12, wherein:
the first contact layer is made of titanium or tungsten;
the first gate dielectric layer and the second gate dielectric layer are made of high dielectric constant material;
the first dielectric layer and the second dielectric layer are made of one of silicon oxide and low dielectric constant material;
the first metal gate and the second metal gate are made of copper, tungsten, aluminum, or silver; and
the third dielectric layer is made of silicon nitride.

### Claim 17

A semiconductor structure, comprising:
a semiconductor substrate having a plurality of first doped regions and a plurality of second doped regions;
a first dielectric layer on the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
at least one first gate dielectric layer on the semiconductor substrate;
a first metal gate on the first gate dielectric layer;
a plurality of second gate dielectric layers;
a second metal gate on each of the second gate dielectric layers;
a third dielectric layer on the second metal gate;
a first contact layer electrically contacting with the first metal gate and the first doped region simultaneously; and
a second contact layer electrically contacting with the second doped region,
wherein the first contact layer and the second contact layer are formed by:
forming an opening to expose at least one first metal gate and at least one first doped region, and a fifth opening to expose the second doped region simultaneously; and
filling the fourth opening and the fifth opening with a metal material.

### Claim 18 (depends on 17)

The semiconductor structure according to claim 17, wherein:
the first contact layer is used as a share contact structure; and
the second contact layer is used as a self-aligned contact structure.

### Claim 19 (depends on 17)

The semiconductor structure according to claim 17, wherein:
the second contact layer is isolated with the second metal gates by the third dielectric layers

### Claim 20 (depends on 17)

The semiconductor structure according to claim 17, wherein:
the first contact layer and the second contact layer are made of titanium or tungsten.