# US 2014/0191335 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2014/0191335 A1
- Document ID: US20140191335A1
- Status: Published application
- Kind: A1
- Application number: 13/812,941
- Filed: 2012-08-27
- Published: 2014-07-10
- Earliest claimed: 2012-07-25
- Assignees: The Institute of Microelectronics Chinese Academy of Science
- Inventors: Huaxiang Yin; Changliang Qin; Xiaolong Ma; Qiuxia Xu; Dapeng Chen
- Web page: https://patentgrep.com/patent/US20140191335A1

## CPC

- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/794: {comprising conductive materials, e.g. silicided source, drain or gate electrodes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of fins located on a substrate and extending along a first direction;
a plurality of gate stack structures extending along a second direction and across each of the fins;
a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein;
a plurality of channel regions located in the fins below the gate stack structures; and
characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the material for the fins is different from that for the stress layers.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the fins are made of a material selected from Si, SiGe, SiSn, GeSn, Si:C, Si:H and SiGe:C, or combinations thereof, and the stress layers are made of a Si alloy material selected from SiGe, SiSn, GeSn, Si:C, Si:H and SiGe:C, or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate stack structures each comprises a gate insulating layer formed of high-K materials and a gate material layer formed of metallic materials.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the connected parts are of a shape of Σ, C, and D, or combinations thereof.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein a metal silicide is formed in/on the source and drain regions.

### Claim 7

A method of manufacturing a semiconductor device, comprising:
forming a plurality of fin structures extending along a first direction on a substrate;
forming a plurality of gate stack structures extending along a second direction and across each of the fins;
etching the fin structures on both sides of the gate stack structures to form source and drain trenches and to make the source and drain trenches have connected parts below the gate stack structures, the connected parts enclosing channel regions;
growing stress layers epitaxially in the source and drain trenches; and
forming source and drain regions in the stress layers.

### Claim 8 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein the material for the fins is different from that for the stress layers.

### Claim 9 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, wherein the fins are made of a material selected from Si, SiGe, SiSn, GeSn, Si:C, Si:H and SiGe:C, or combinations thereof, and the stress layers are made of a Si alloy material selected from SiGe, SiSn, GeSn, Si:C, Si:H and SiGe:C, or combinations thereof.

### Claim 10 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein the gate stack structures each comprises a gate insulating layer formed of high-K materials and a gate material layer formed of metallic materials.

### Claim 11 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein the connected parts are of a shape of Σ, C, and D, or combinations thereof.

### Claim 12 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the connected parts further comprises:
etching the fin structures on both sides of the gate stack structures to form first trenches having vertical sidewalls; and
etching the sidewalls of the first trenches to form second trenches, wherein the second trenches have connected parts below the gate stack structures, and said connected parts enclose the channel regions.

### Claim 13 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein after forming the source and drain regions, the method further comprises forming a metal silicide in/on the source and drain regions.

### Claim 14 (depends on 7)

The method of manufacturing a semiconductor device according to claim 7, wherein after forming the source and drain regions, the method further comprises:
forming an interlayer dielectric layer over the entire device;
performing etching to remove the gate stack structures to form gate trenches; and
depositing a gate insulating layer formed of high-K materials and a gate material layer formed of metallic materials in the gate trenches.