# US 2014/0191334 A1 · Stacked power semiconductor device using dual lead frame > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0191334 A1 - Document ID: US20140191334A1 - Status: Published application - Kind: A1 - Application number: 13/734,201 - Filed: 2013-01-04 - Published: 2014-07-10 - Earliest claimed: 2013-01-04 - Assignees: Alpha and Omega Semiconductor Incorporated - Inventors: Yan Xun Xue; Yueh-Se Ho; Lei Shi; Jun Lu; Liang Zhao - Web page: https://patentgrep.com/patent/US20140191334A1 ## CPC - H10W 90/811: {Multiple chips on leadframes} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/837: {comprising vertical IGFETs} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices - H10W 72/07336: {Soldering or alloying} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07636: {Soldering or alloying} - H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07653: {changes in shapes} - H10W 72/631: {Shapes of strap connectors} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip. ## Claims ### Claim 1 A stacked power semiconductor device with dual lead frame, comprising: a bottom lead frame comprising a first bottom base, a second and a third bottom bases adjacent to the first bottom base and separated from the first bottom base; a mounting clip comprising an extending part bending downward; a top lead frame comprising a first top base and a second top base adjacent to and separated from the first top base; a first semiconductor chip comprising a first electrode and a second electrode at a front side of the first semiconductor chip and a third electrode at a back side of the first semiconductor chip; and a second semiconductor chip comprising a first electrode and a second electrode at a front side of the second semiconductor chip and a third electrode at a back side of the second semiconductor chip; wherein the first semiconductor chip is flip-chip mounted on the bottom lead frame with the first and second electrodes respectively connected to the first bottom base and the second bottom base of the bottom lead frame, wherein the mounting clip is stacked on the first semiconductor chip with a bottom surface of the mounting clip connected to the third electrode located on the back side of the first semiconductor chip, with the downward extending part of the mounting clip extending to and connecting to a top surface of the third bottom base of the bottom lead frame, and wherein the second semiconductor chip is flip-chip mounted on a top surface of the mounting clip with the first electrode connected to the mounting clip and the second electrode extending beyond an edge of the mounting clip, wherein a bonding wire electrically connecting the second electrode of the second semiconductor chip to a bottom surface of the second top base of the top lead frame facing against the third electrode of the first semiconductor chip, wherein the first top base of the top lead frame is stacked on and electrically connected to the third electrode of the second semiconductor chip. ### Claim 2 (depends on 1) The stacked power semiconductor device with dual lead frame of claim 1, wherein the second electrode of the second semiconductor chip extending beyond the edge area of the mounting clip is electrically connected to the second top base of the top lead frame. ### Claim 3 (depends on 2) The stacked power semiconductor device with dual lead frame of claim 2, wherein at least a portion of the second top base is located above and beyond the edge of the mounting clip. ### Claim 4 (canceled) ### Claim 5 (depends on 2) The stacked power semiconductor device with dual lead frame of claim 2, wherein each of the first top base and the second top base of the top lead frame comprises an extending part bending downwards, and wherein the extending parts extend to a surface coplanar to a bottom surface of the bottom lead frame. ### Claim 6 (depends on 2) The stacked power semiconductor device with dual lead frame of claim 2, wherein the first semiconductor chip is a low-side (LS) MOSFET, and the second semiconductor chip is a high-side (HS) MOSFET, and wherein the first electrode of the first and second semiconductor chip is a source electrode, the second electrode of the first and second semiconductor chip is a gate electrode, and the third electrode of the first and second semiconductor chip is a drain electrode. ### Claim 7 (depends on 5) The stacked power semiconductor device with dual lead frame of claim 5, wherein the extending part of the first top base is disposed at a first side of the stacked power semiconductor device and the extending part of the mounting clip is disposed at a second side of the stacked power semiconductor device opposite to the first side. ### Claim 8 (depends on 5) The stacked power semiconductor device with dual lead frame of claim 5, wherein the extending parts of the first and second top bases terminated at an edge of a plastic molding body encapsulating at least part of the bottom lead frame, the mounting clip, the top lead frame and the first and second semiconductor chips. ### Claim 9 (depends on 1) The stacked power semiconductor device with dual lead frame of claim 1, wherein a top surface of the first top base of the top lead frame is exposed through a top surface of the plastic molding body.