# US 2014/0191333 A1 · Method of protecting an interlayer dielectric layer and structure formed thereby

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- Number: US 2014/0191333 A1
- Document ID: US20140191333A1
- Status: Published application
- Kind: A1
- Application number: 13/735,949
- Filed: 2013-01-07
- Published: 2014-07-10
- Earliest claimed: 2013-01-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Wei CHANG; Yi-An LIN; Neng-Kuo CHEN; Sey-Ping SUN; Clement Hsingjen WANN; Yu-Lien HUANG
- Web page: https://patentgrep.com/patent/US20140191333A1

## CPC

- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

## Claims

### Claim 1

A semiconductor device comprising:
a first gate structure;
a second gate structure;
an interlayer dielectric (ILD) layer over a substrate for electrically insulating the first gate structure from the second gate structure;
a silicide layer between the ILD and the substrate; and
a protective layer on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, wherein a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the protective layer has a thickness of about 10 nanometers (nm) to about 20 nm.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the protective layer comprises silicon nitride (SiN), silicon carbide (SiC) or silicon carbon nitride (SiCN).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first electrode layer in the first gate structure; and
a second electrode layer in the second gate structure, wherein the protective layer has a different etch selectivity than the first electrode layer and the second electrode layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the protective layer is about 20% to about 100% of a thickness of the ILD layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a width of the ILD layer ranges from about 25 nanometers (nm) to about 75 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the first gate structure or the second gate structure is a replacement gate structure.

### Claim 8

A semiconductor device comprising:
a substrate;
a first gate structure on the substrate;
a second gate structure on the substrate;
an interlayer dielectric (ILD) layer for electrically insulating the first gate structure from the second gate structure on the substrate, wherein a top surface of the ILD layer is lower than top surfaces of the first and second gate structures;
a contact etch stop layer (CESL) surrounding the ILD layer; and
a protective layer on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, wherein a top surface of the protective layer is level with the top surfaces of the first and second gate structures, and a width of the protective layer is equal to a width of the ILD layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the protective layer has a thickness of about 10 nanometers (nm) to about 20 nm.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the protective layer comprises silicon nitride (SiN), silicon carbide (SiC) or silicon carbon nitride (SiCN).

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising:
a first electrode layer in the first gate structure; and
a second electrode layer in the second gate structure, wherein the protective layer has a different etch selectivity than the first electrode layer and the second electrode layer.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a thickness of the protective layer is about 20% to about 100% of a thickness of the ILD layer.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising:
a first spacer between the first gate structure and the ILD layer; and
a second spacer between the second gate structure and the ILD layer.

### Claim 14

(canceled)

### Claim 15

A method of protecting an interlayer dielectric (ILD) layer, the method comprising:
forming a gate structure over a substrate;
forming a silicide region adjacent to the gate structure;
forming the ILD layer over the substrate;
forming a cavity in a top portion of the ILD layer, wherein the ILD layer is between a bottom of the cavity and the silicide region;
filling the cavity with a protective layer formed over the ILD layer and the gate structure; and
planarizing the protective layer, wherein a top surface of the planarized protective layer is level with a top surface of the gate structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming the cavity in the top portion of the ILD layer comprises etching the ILD layer to a pre-determined depth.

### Claim 17 (depends on 15)

The method of claim 15, wherein the forming the cavity comprises forming the cavity having a depth of about 10 nanometers (nm) to about 20 nm.

### Claim 18 (depends on 15)

The method of claim 15, wherein the filling the cavity comprises forming the protective layer comprising silicon nitride (SiN), silicon carbide (SiC) or silicon carbon nitride (SiCN).

### Claim 19 (depends on 15)

The method of claim 15, wherein the filling the cavity comprises forming the protective layer having a different etch selectivity than the ILD layer.

### Claim 20 (depends on 15)

The method of claim 15, further comprising performing a metallization process after the planarization of the protective layer.

### Claim 21 (depends on 1)

The semiconductor device of claim 1, wherein a width of the protective layer is equal to a width of the ILD layer.