# US 2014/0191331 A1 · Transistor and Its Method of Manufacture

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- Number: US 2014/0191331 A1
- Document ID: US20140191331A1
- Status: Published application
- Kind: A1
- Application number: 14/129,630
- Filed: 2012-06-22
- Published: 2014-07-10
- Earliest claimed: 2011-06-27
- Assignees: Pragmatic Printing Ltd.
- Inventors: Richard Price; Scott White
- Web page: https://patentgrep.com/patent/US20140191331A1

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/903: {comprising field effect technology}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/0241: {using liquid deposition, e.g. printing}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate}
- H10P 14/40: of conductive or resistive materials
- H10P 50/73: {using masks for insulating materials}
- H10P 76/202: {for lift-off processes}
- H10W 20/0698: {Local interconnections}
- H10W 20/43: Layouts of interconnections
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region.

## Claims

### Claim 1

A method of manufacturing a transistor, the method comprising:
providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material;
forming at least one layer of resist material over said regions to form a covering of resist material over said regions;
forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of electrically conductive material, said first portion separating a second portion of the region of electrically conductive material from a third portion of the region of electrically conductive material;
removing resist material located under said depression so as to form a first window, through said covering of resist material, exposing said first portion of the region of electrically conductive material;
removing said first portion of the region of electrically conductive material to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion of the region of electrically conductive material to the third portion of the region of electrically conductive material;
forming a layer of dielectric material over the exposed connecting portion of the region of semiconductive material; and
depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the region of electrically conductive material,
whereby said second and third portions of the region of electrically conductive material provide a source terminal and a drain terminal, respectively, and
whereby the layer of electrically conductive material provides a gate terminal to which a potential may be applied to control a conductivity of the connecting portion of the region of semiconductive material connecting the second and third portions of the region of electrically conductive material.

### Claim 2 (depends on 1)

A method in accordance with claim 1, wherein said forming at least one layer of resist material comprises forming a first layer of a first resist material over said regions, and forming a second layer of a second resist material over the first layer.

### Claim 3 (depends on 2)

A method in accordance with claim 2, wherein said first resist material is a lift-off resist material.

### Claim 4 (depends on 2)

A method in accordance with claim 2, wherein said second resist material is an imprintable resist material.

### Claim 5 (depends on 1)

A method in accordance with claim 1, wherein forming said depression in a surface of the covering of resist material comprises forming said depression by imprinting using an imprinting tool.

### Claim 6 (depends on 4)

A method in accordance with claim 4, wherein forming said depression in a surface of the covering of resist material comprises forming said depression by imprinting using an imprinting tool, and wherein said surface of the covering of resist material is a surface of the second layer of resist material.

### Claim 7 (depends on 6)

A method in accordance with claim 6, wherein forming said depression in a surface of the covering of resist material is performed at the same time as forming the second layer of the second resist material.

### Claim 8 (depends on 6)

A method in accordance with claim 6, wherein forming said depression in a surface of the covering of resist material is performed after forming the second layer of the second resist material.

### Claim 9 (depends on 1)

A method in accordance with claim 1, wherein forming a layer of dielectric material over the exposed connecting portion of the region of semiconductive material comprises depositing dielectric material at least inside the first window to form the layer of dielectric material, and wherein the method further comprises:
removing resist material at least from around said first window so as to expose the second and third portions of the region of electrically conductive material.

### Claim 10 (depends on 9)

A method in accordance with claim 9, further comprising undercutting the covering of resist material around the first window before said depositing of dielectric material so as to expose a part of an upper surface of the second portion of the region of electrically material adjacent the connecting portion and to expose a part of an upper surface of the third portion of the region of electrically material adjacent the connecting portion of the region of semiconductive material.

### Claim 11 (depends on 10)

A method in accordance with claim 10, wherein said depositing of dielectric material is arranged such that the layer of dielectric material at least partly covers the exposed part of the upper surface of the second portion of the re ion of electrically conductive material and the exposed part of the upper surface of the third portion of the region of electrically conductive material.

### Claim 12 (depends on 10)

A method in accordance with claim 10, wherein said forming at least one layer of resist material over said regions to form a covering of resist forming a first layer of a first resist material over said regions and forming a second layer of a second resist material over the first layer, and wherein undercutting the covering of resist material comprises forming at least one undercut in the first layer.

### Claim 13 (depends on 10)

A method in accordance with claim 10, further comprising removing resist material to widen said first window after said undercutting but before said depositing of dielectric material.

### Claim 14 (depends on 10)

A method in accordance with claim 10, further comprising removing resist material to widen said first window at the same time as said undercutting.

### Claim 15 (depends on 5)

A method in accordance with claim 5, wherein the imprinting tool comprises a plurality of imprint features each raised a respective height above a base surface of the imprinting tool.

### Claim 16 (depends on 15)

A method in accordance with claim 15, wherein the plurality of imprint features comprises a first imprint feature raised a first height above the base surface, and wherein forming said depression comprises forming the depression with the first imprint feature, such that the depression initially has a depth substantially equal to the first height.

### Claim 17 (depends on 16)

A method in accordance with claim 16, wherein the plurality of imprint features comprises a second imprint feature raised a second height above the base surface, the second height being greater than the first height, and the second imprint feature being arranged to define a perimeter of the transistor, and the method further comprising using the second imprint feature to form a second depression in the surface of the covering of resist material, said second depression extending around the first, second, and third portions of said region of electrically conductive material.

### Claim 18 (depends on 17)

A method in accordance with claim 17, wherein the imprint tool comprises first and second base regions arranged inside the second imprint feature and separated by the first imprint feature, the base regions defining the positions of the second and third portions of the region of electrically conductive material.

### Claim 19 (depends on 17)

A method in accordance with claim 17, the method further comprising:
removing resist material located under the second depression so as to form a second window, through said covering of resist material, exposing a perimeter portion of the region of electrically conductive material surrounding the first, second, and third portions of the region of electrically conductive material;
removing the perimeter portion of the region of electrically conductive material to expose an underlying perimeter portion of the region of semiconductive material; and
removing the perimeter portion of the region of semiconductive material to expose an underlying perimeter portion of the substrate, whereby the perimeter portion of the substrate surrounds the transistor.

### Claim 20 (depends on 19)

A method in accordance with claim 19, the method further comprising:
forming a covering layer of dielectric material to cover said underlying perimeter portion of the substrate, said second and third portions of the region of electrically conductive material, and said connecting portion of the region of semiconductive material;
forming a layer of photoresist material over said covering layer;
exposing the layer of photoresist material to radiation from a radiation source such that the second and third portions of the region of electrically conductive material at least partially shield first and second portions of the layer of photoresist material, located above the second and third portions of the region of electrically conductive material respectively, from said radiation;
developing the layer of photoresist material to remove said first and second portions of the layer of photoresist material to expose underlying portions of the covering layer of dielectric material; and
removing said underlying portions of the covering layer of dielectric material to expose parts of the second and third portions of the region of electrically conductive material,
whereby electrical connections can be made, through the covering layer of dielectric material, to the exposed parts of the second and third portions of the region of electrically conductive material.

### Claim 21 (depends on 20)

A method in accordance with claim 20, further comprising:
removing remaining photoresist material after exposing said parts of the second and third portions of the region of electrically conductive material.

### Claim 22 (depends on 21)

A method in accordance with claim 21, wherein said removing remaining photoresist material exposes a channel covering portion of the covering layer of dielectric material, the channel covering portion covering at least said connecting portion of the region of semiconductive material, and wherein the method further comprises forming a gate terminal on the channel covering portion of the covering layer of dielectric material.

### Claim 23 (depends on 19)

A method in accordance with claim 19, further comprising:
forming undercuts in walls of the resist material defining the first and second windows; depositing dielectric material at least inside the first and second windows to cover at least the underlying perimeter portion of the substrate and said connecting portion of the region of semiconductive material; and
removing resist material to expose at least parts of the second and third portions of the region of electrically conductive material.

### Claim 24 (depends on 23)

A method in accordance with claim 23, further comprising forming a gate terminal on the dielectric material covering said connecting portion of the region of semiconductive material.

### Claim 25 (depends on 1)

A transistor manufactured using a method in accordance with claim 1.

### Claim 26 (depends on 25)

An electronic circuit or logic gate comprising at least one transistor in accordance with claim 25.

### Claim 27 (depends on 1)

An electrical circuit manufactured using a method in accordance with claim 1.

### Claim 28 (depends on 25)

A programmable transistor array comprising a plurality of transistors, each in accordance with claim 25, and having been formed on a common substrate.

### Claim 29 (depends on 25)

A programmable logic array comprising a plurality of logic gates, each logic gate comprising at least one respective transistor in accordance with claim 25, and wherein the respective transistors are formed on a common substrate.

### Claim 30 (depends on 28)

An array in accordance with claim 28, further comprising a covering of dielectric material formed over the plurality of transistors formed on the common substrate.

### Claim 31 (depends on 30)

An array in accordance with claim 30, further comprising a plurality of windows formed in the covering of dielectric material to expose a plurality of terminals of the plurality of transistors so as to enable selected interconnections to be made between the exposed terminals.

### Claim 32 (depends on 28)

An electronic circuit comprising an array in accordance with claim 28, and a plurality of electrical tracks arranged to provide interconnections between selected transistor terminals.

### Claim 33 (depends on 1)

A method of forming an electronic circuit, the method comprising manufacturing an array of a plurality of transistors on a common substrate using a method in accordance with claim 1, forming a covering of dielectric material over the array of transistors, forming a plurality of windows in the covering of dielectric material, each window exposing at least a portion of a terminal of a respective transistor, and selectively forming interconnections between said exposed portions of terminals.

### Claim 34 (depends on 33)

A method in accordance with claim 33, wherein selectively forming interconnections between said exposed portions of terminals comprises printing conductive material.

### Claim 35 (depends on 34)

An electronic circuit manufactured using a method in accordance with claim 34.

### Claim 36

A transistor comprising:
a substrate;
a region of semiconductive material supported by the substrate;
a source terminal and a drain terminal, wherein each of the source terminal and the drain terminal is supported by the region of semiconductive material, and wherein the source and drain terminals are connected by a connecting portion of the region of semiconductive material;
a layer of dielectric material deposited so as to cover at least a portion of said connecting portion of the region of semiconductive material; and
a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material, the layer of dielectric material electrically isolating the layer of conductive material from the source and drain terminals, and the layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the connecting portion of the region of semiconductive material connecting the source and drain terminals.

### Claim 37

(canceled)